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Re: Cyclone 10LP 1.8V specifications
After a long time, I am able to follow up on this topic. I will try to rephrase my question: At 1.8V, the IO has JEDEC8-7 compliance. JESD8-7A output is 0.45V (low) and VDD-0.45V (high). However, I have found several other logic circuits claiming to be "1.8V LVCMOS" or "1.8V LVTTL" compatible, with stricter IO thresholds. This other logic require 0.3V (low) and 0.8*VDD = VDD-0.36V (high). The question is what spec is that other logic, and is it actually compatible with the Cyclone 10LP (JESD8-7)? Ivar Svendsen.859Views0likes0CommentsRe: Cyclone 10LP Power requirements
Hi, Somehow this thread deviated from the original question: Using 3.3V Active Serial configuration, bank 1 is bound to 3.3V as it is the configuration voltage. Can I still use 1.5V on banks 5, 6 and 8? The documentation is somewhat unclear if all banks containing some IO pins (1, 5, 6, and 8.) 😎are bound by the same IO voltage standard. They contain configuration pins that are either optional or not used with Active Serial configuration. The following experiment suggests that the configuration voltage standard (set by the MSEL pins) apply to the banks of the active configuration scheme only: 1. Create a Quartus project, selecting the target device 2. Using the pin planner, assign the desired voltage standard to each bank. 3. Using the "Device and Pin options" dialog, select the configuration scheme, configuration device IO voltage. I did also select Force VCCIO to be compatible with the configuration IO voltage. 4. Run the IO Assignment Analysis task (Compile design > Analysis & Synthesis) In my case I selected 3.3V Active Serial, and tried selecting 1.8V to all banks (1-8). The IO assignment analysis fails, saying I cannot have 1.8V on bank 1. This makes sense, as the Active Serial IO pins use that bank. Selecting 3.3V to bank 1 and 1.8V to the other banks, the IO assignment analysis succeeds. This take this as confirmation to my original question. Unless this is not correct, I consider the case closed. Regards, Ivar Svendsen.1.6KViews0likes0CommentsRe: Cyclone 10LP Power requirements
Hi, Somehow this thread deviated from the original question: Using 3.3V Active Serial configuration, bank 1 is bound to 3.3V as it is the configuration voltage. Can I still use 1.5V on banks 5, 6 and 8? The documentation is somewhat unclear if all banks containing some IO pins (1, 5, 6 and 😎 are bound by the same IO voltage standard. They contain configuration pins that are either optional or not used with Active Serial configuration. The following experiment suggests that the configuration voltage standard (set by the MSEL pins) apply to the banks of the active configuration scheme only: 1. Create a Quartus project, selecting the target device 2. Using the pin planner, assign the desired voltage standard to each bank. 3. Using the "Device and Pin options" dialog, select the configuration scheme, configuration device IO voltage. I did also select Force VCCIO to be compatible with the configuration IO voltage. 4. Run the IO Assignment Analysis task (Compile design > Analysis & Synthesis) In my case I selected 3.3V Active Serial, and tried selecting 1.8V to all banks (1-8). The IO assignment analysis fails, saying I cannot have 1.8V on bank 1. This makes sense, as the Active Serial IO pins use that bank. Selecting 3.3V to bank 1 and 1.8V to the other banks, the IO assignment analysis succeeds. This take this as confirmation to my original question. Regards, Ivar Svendsen.1.6KViews0likes0CommentsCyclone 10LP 1.8V specifications
Hello, I am reviewing a design for digital IO compatibility. The Cyclone 10LP Datasheet specify VOH=VCCIO-0.45V and VOL=0.45V at 2 mA. This seem incompatible with some 1.8V devices that require 20% for VIL (0.36V). EDIT: Reading further, the Core Fabric handbook claims JEDEC8-7 compliance, and names both 1.8V LVTTL and LVCMOS. I guess the Cyclone 10LP may successfully those other chips, provided the current drawn is less than 100 uA (limit according to JESD8-7A). Regards, Ivar Svendsen.972Views0likes3CommentsRe: Cyclone 10LP Power requirements
Hello, I guess I need to make a board and try. It is still not very clear. The device datasheet lists 5 recommended operation voltage ranges (1.2V up to 3.3V), but there is no information on how the chip decide which range the power supply must be stable within, before the end of POR (nSTATUS is released). There are also no information to what constitute "without plateau". Regards, Ivar Svendsen.1.7KViews0likes0CommentsCyclone 10LP Power requirements
Hello, I am planning to use Cyclone 10LP (F484 BGA) with a 3.3V Active Serial configuration scheme. All Active Serial configuration pins are part of Bank 1. I hope to be able to use banks 5, 6 and 8 with 2.5V. However, those banks contains the MSEL, CONF_DONE, INIT_DONE, CRC_ERROR and parallel IO pins. I have been reading the Cyclone 10LP handbooks and guides, but it is still unclear exactly what is the powerup requirements. Handbook chapter 6.2.1 says: "After device power up, the device does not release nSTATUS until VCCINT, VCCA, and VCCIO (for I/O banks in which the configuration and JTAG pins reside) are above the POR trip point of the device. • VCCINT and VCCA are monitored for brown-out conditions after device power up. • VCCA is the analog power to the phase-locked loop (PLL)." The actual POR trip point is not defined anywhere that I can find (not in the device datasheet). Also, it is not clear which banks are involved. By selecting 3.3V Active Serial, is the banks mentioned (5, 6, 😎😎 😎locked to 3.3V, even if their IO are not part of the actual configuration? I appreciate any insight to this. Regards, Ivar Svendsen1.9KViews0likes6CommentsRe: FPGA to HPS Peripheral address mapping
Yes, I want to access HPS peripherals from the FPGA. I have learned that the "Address Span Extender" component is doing what I want: To map multiple windows into the HPS address space from the FPGA. I think this has solved the challenge.857Views0likes0CommentsFPGA to HPS Peripheral address mapping
Hello, I am looking into the Cyclone 5 SoC. The hard processor system (HPS) have a peripheral region from 0xFC000000 - 0xFFFFFFFF. This region is accessible to the FPGA fabric through the FPGA-to-HPS (F2H) bridge. On the FPGA side I am forced to use a NiosII processor with MMU for legacy reasons. Also, I am restricted to Quartus 17.0 (SIL requirement) Connecting the data master directly to the F2H bridge will not work, because any address in the peripheral region is in the bypass-MMU virtual range. Adding an Avalon-MM bridge will not work either: For example, trying to map the bridge at 0x04000000 - 0x04FFFFFF as seen by the NiosII processor. First, the HPS cannot be mapped to address 0xFC000000, it is not a valid Avalon-MM slave address. Second, the HPS must be mapped at address 0, because it is address space is 32-bit wide on the 32-bit bus. Trying another offset, QSys say the end address overflows. Is there any other address-translation bridges that may be used? Regards, Ivar Svendsen901Views0likes4CommentsHLS Compiler
Hi, I am trying to download the HLS compiler, to use with Quartus Lite. The HLS compiler page directs me to the FPGA software download center, but from there I am unable to find the link to start download. I have already registered for an Intel account, and I am logged in. Still, there is a blue banner across my screen telling me that I can log in to have additional results. Clicking the "sign in" link to sign in again makes no difference. Generally, the software center is a crappy experience. Could anyone please direct me to a way to download the HLS compiler, or fix the download center? Much appreciated, my work progress is at halt until Intel fixes this.923Views0likes3Comments