MSenk1
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Problem with Fitter LL Ethernet 10G R core rx/tx_serial I/O
Hallo, I'm using the LL Ethernet 10G R core from Intel. When I use the sample design it works fine. When I start adding more functions after a while the fitter (Quartue 21.2/3)gives me this error message: Extra Info(13133): Output port's "VOP[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf". Extra Info(13134): Input port's "DATAA[0]" node name is "tx_eth_serial_data[0]". Extra Info(12877): Output port "VOP[0]" of "HSSI_PMA_TX_BUF" can connect to: Extra Info(12878): Port "IN[0]" of "IO_OUTPUT_BUFFER". Extra Info(13133): Output port's "COMBOUT[0]" node name is "rx_eth_serial_data[0]". Extra Info(13134): Input port's "RX_P_BIDIR_IN[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf". Extra Info(12879): Input port "RX_P_BIDIR_IN[0]" of "HSSI_PMA_TX_BUF" can connect to: Extra Info(12880): Port "OUT[0]" of "IO_INPUT_BUFFER". Extra Info(13133): Output port's "COMBOUT[0]" node name is "rx_eth_serial_data[0]". Extra Info(13134): Input port's "RXP[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll". Extra Info(12879): Input port "RXP[0]" of "HSSI_PMA_CDR_PLL" can connect to: Extra Info(12880): Port "OUT[0]" of "IO_INPUT_BUFFER". Extra Info(13133): Output port's "COMBOUT[0]" node name is "rx_eth_serial_data[0]". Extra Info(13134): Input port's "RXP[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_buf.inst_twentynm_hssi_pma_rx_buf". Extra Info(12879): Input port "RXP[0]" of "HSSI_PMA_RX_BUF" can connect to: Extra Info(12880): Port "OUT[0]" of "IO_INPUT_BUFFER". Error(11216): Output port "VOP" of "HSSI_PMA_TX_BUF" cannot connect to PLD port "DATAA" of "LE_COMB" for node "tx_eth_serial_data[0]". Extra Info(13133): Output port's "VOP[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf". Extra Info(13134): Input port's "DATAA[0]" node name is "tx_eth_serial_data[0]". Extra Info(12877): Output port "VOP[0]" of "HSSI_PMA_TX_BUF" can connect to: Extra Info(12878): Port "IN[0]" of "IO_OUTPUT_BUFFER". Error(11215): Input port "RX_P_BIDIR_IN" of "HSSI_PMA_TX_BUF" cannot connect to PLD port "COMBOUT" of "LE_COMB" for node "rx_eth_serial_data[0]". Extra Info(13133): Output port's "COMBOUT[0]" node name is "rx_eth_serial_data[0]". Extra Info(13134): Input port's "RX_P_BIDIR_IN[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf". Extra Info(12879): Input port "RX_P_BIDIR_IN[0]" of "HSSI_PMA_TX_BUF" can connect to: Extra Info(12880): Port "OUT[0]" of "IO_INPUT_BUFFER". Error(11215): Input port "RXP" of "HSSI_PMA_CDR_PLL" cannot connect to PLD port "COMBOUT" of "LE_COMB" for node "rx_eth_serial_data[0]". Extra Info(13133): Output port's "COMBOUT[0]" node name is "rx_eth_serial_data[0]". Extra Info(13134): Input port's "RXP[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll". Extra Info(12879): Input port "RXP[0]" of "HSSI_PMA_CDR_PLL" can connect to: Extra Info(12880): Port "OUT[0]" of "IO_INPUT_BUFFER". Error(11215): Input port "RXP" of "HSSI_PMA_RX_BUF" cannot connect to PLD port "COMBOUT" of "LE_COMB" for node "rx_eth_serial_data[0]". Extra Info(13133): Output port's "COMBOUT[0]" node name is "rx_eth_serial_data[0]". Extra Info(13134): Input port's "RXP[0]" node name is "ethernet_top_top_0|CNL[0].wrapper_inst|baser_inst|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma|gen_twentynm_hssi_pma_rx_buf.inst_twentynm_hssi_pma_rx_buf". Extra Info(12879): Input port "RXP[0]" of "HSSI_PMA_RX_BUF" can connect to: Extra Info(12880): Port "OUT[0]" of "IO_INPUT_BUFFER". Error(16297): An error has occurred while trying to initialize the plan stage. I started several times from scratch but after a while I get this error message and I found not way to return. regards MichaelCyclone 10 Low Latency 10Gbase-R core has a problem to fit the serial tx/rx signals
Hallo, I'm using the low latency 10GBase-R core on a Cyclone 10. When I started the project the compiler worked fine. After a some iterations in my project the compile didn't fit anymore. For the error message see attachment. I tried to revered all changes but I never got it to work again. I started again from scratch, but after a while I run into the same issue. Do you have any idea what could cause such an error message? regards MichaelProblem with Signal Tap Logic Analyzer
Hi, I'm using Quartus 21.2. When I use the signal tap logic analyser I get a crash. The FPGA works fine with the loaded content. But the logic analyser crashes with this message: Problem Details Error: Internal Error: Sub-system: CHI, File: /quartus/sld/chi/chi_aji_hierarchical_access.cpp, Line: 491 Can't operate on nodes that haven't been opened. Stack Trace: Quartus 0x1deaf: CHI_AJI_HIERARCHICAL_ACCESS::lock_node + 0x2f (sld_chi) Quartus 0x8188: CHI_CONTROL_NODE2::batch_access + 0x28 (sld_chi) Quartus 0xa1bf: CHI_CONTROL_NODE_STP_V6::get_node_crc_value + 0x1af (sld_chi) Quartus 0x14d1b: CHI_CONTROL_NODES_SCAN::scan_device + 0x52b (sld_chi) Quartus 0x146dd: CHI_CONTROL_NODES_SCAN::rescan + 0xd (sld_chi) Quartus 0xcea81: SEDQ_INSTANCE_WIDGET::on_update + 0x3d1 (sld_sedq) Quartus 0x2013b6: QObject::event + 0x146 (Qt5Core) Quartus 0x3a0f4: QWidget::event + 0xf34 (Qt5Widgets) Quartus 0xdbc76: QFrame::event + 0x36 (Qt5Widgets) Quartus 0x68c6c: SEDQ_INSTANCE_WIDGET::event + 0x4c (sld_sedq) Quartus 0x1700c: QApplicationPrivate::notify_helper + 0x13c (Qt5Widgets) Quartus 0x14fae: QApplication::notify + 0xa6e (Qt5Widgets) Quartus 0x1d9b88: QCoreApplication::notifyInternal2 + 0xb8 (Qt5Core) Quartus 0x1dc1e8: QCoreApplicationPrivate::sendPostedEvents + 0x228 (Qt5Core) Quartus 0x5999e: qt_plugin_query_metadata + 0x1e8e (qwindows) Quartus 0x226eb6: QEventDispatcherWin32::processEvents + 0x66 (Qt5Core) Quartus 0x59978: qt_plugin_query_metadata + 0x1e68 (qwindows) Quartus 0x1d59b0: QEventLoop::exec + 0x1a0 (Qt5Core) Quartus 0x1d887a: QCoreApplication::exec + 0x14a (Qt5Core) Quartus 0x10c8: qgq_main + 0x88 (qpro) Quartus 0x190b8: msg_main_thread + 0x18 (CCL_MSG) Quartus 0x19781: msg_thread_wrapper + 0x71 (CCL_MSG) Quartus 0x22dc0: mem_thread_wrapper + 0x70 (ccl_mem) Quartus 0x1734d: msg_exe_main + 0x20d (CCL_MSG) Quartus 0x20d6: WinMain + 0x156 (qpro) Quartus 0x16e2: __scrt_common_main_seh + 0x116 (qpro) Quartus 0x17033: BaseThreadInitThunk + 0x13 (KERNEL32) Quartus 0x52650: RtlUserThreadStart + 0x20 (ntdll) End-trace The programmer worked successfully. I tried several simple 2 signal logic analyser, that does not change anything. With Quartus 21.1 I had no problem. What is wrong? regards MichaelQuartus Crash with Internal Error: Sub-system: OPT, File: /quartus/synth/opt/opt_carry_pack.cpp
Hallo, I'm constantly getting this following error. Is there a patch? regards Mike. Version: 20.2.0 Build: 50 Edition: Pro Edition Problem Details Error: Internal Error: Sub-system: OPT, File: /quartus/synth/opt/opt_carry_pack.cpp, Line: 1686 left_input_num + right_input_num <= 4 Stack Trace: Quartus 0x141ed2: opt_prepare_lcells_for_merging + 0x24e (SYNTH_OPT) Quartus 0x142adc: OPT_CARRY_PACK::pack_chains + 0x918 (SYNTH_OPT) Quartus 0x13fb98: OPT_CARRY_PACK::apply_packing_solution + 0xc8 (SYNTH_OPT) Quartus 0xbf044: OPT_CARRY_PACK::pack_carry_chains + 0x1cb30 (SYNTH_OPT) Quartus 0xa191d: opt_run_carry_chain_packer + 0x75 (SYNTH_OPT) Quartus 0x21670: FTM_ROOT_IMPL::postprocess + 0xd0 (SYNTH_FTM) Quartus 0x1b695: FTM_ROOT_IMPL::start_normal_flow + 0xd95 (SYNTH_FTM) Quartus 0x19bed: FTM_ROOT_IMPL::start + 0x1dd (SYNTH_FTM) Quartus 0x18c7f: FTM_ROOT::start + 0xdf (SYNTH_FTM) Quartus 0x2a3b5: SCL_SYN_HIER::do_tech_mapping + 0x1c5 (SYNTH_SCL) Quartus 0x5228: scl_run_ftm + 0x78 (SYNTH_SCL) Quartus 0xc7a8a: SYNTH::QIS::SYNTHESIS_FLOW::ftm + 0x5a (synth_qis) Quartus 0xcaee5: SYNTH::QIS::SYNTHESIS_FLOW::run_current_phase + 0x1d5 (synth_qis) Quartus 0xcb4ed: SYNTH::QIS::SYNTHESIS_FLOW::run_full_flow + 0x30d (synth_qis) Quartus 0x59517: QIS_RTL_STAGE::IMPL::synthesize + 0x4c7 (synth_qis) Quartus 0x1bd95: qis_synthesize + 0x1d5 (synth_qis) Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86) Quartus 0x17c4d: TclEvalEx + 0x9ed (tcl86) Quartus 0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86) Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86) Quartus 0x156f6: qexe_evaluate_tcl_script + 0x4e6 (comp_qexe) Quartus 0x145e3: qexe_do_tcl + 0x4b3 (comp_qexe) Quartus 0x1acae: qexe_run_tcl_option + 0x5ee (comp_qexe) Quartus 0x18ef1: QCU::DETAIL::intialise_qhd_and_run_qexe + 0xa1 (comp_qcu) Quartus 0x2b312: qcu_run_tcl_option + 0x2f2 (comp_qcu) Quartus 0x13cc: qsyn2_tcl_process_default_flow_option + 0x1dc (quartus_syn) Quartus 0x1a5b0: qexe_run + 0x460 (comp_qexe) Quartus 0x1b6ea: qexe_standard_main + 0x26a (comp_qexe) Quartus 0x3039: qsyn2_main + 0x129 (quartus_syn) Quartus 0x158d8: msg_main_thread + 0x18 (CCL_MSG) Quartus 0x16f81: msg_thread_wrapper + 0x71 (CCL_MSG) Quartus 0x21050: mem_thread_wrapper + 0x70 (ccl_mem) Quartus 0x14e5d: msg_exe_main + 0x20d (CCL_MSG) Quartus 0x4924: __scrt_common_main_seh + 0x11c (quartus_syn) Quartus 0x17bd3: BaseThreadInitThunk + 0x13 (KERNEL32) Quartus 0x6ce50: RtlUserThreadStart + 0x20 (ntdll) End-trace Executable: quartus_syn Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 20.2.0 Build: 50 Edition: Pro EditionRe: How do I add the 'altera_merlin_slave_translator' to my Quartus 20.2 Platform Designer?
Thank you, I learnt that I have to use the Avalon_clock_crossing_bridge instead of the older 'slave_translator'. I had to generate my own read_data_valid, but finally it works. A hint in the documentation that the older 'merlin' based connectors are replace by the Avalon_clock_crossing_bridge would have help a lot. Thanks MikeHow do I add the 'altera_merlin_slave_translator' to my Quartus 20.2 Platform Designer?
Hallo, I'm using Quartus 20.2. In my design in the Platform Designer I would like to add the 'altera_merlin_slave_translator'. I can find it in the 'intel_fpga_pro/ip/altera/... but not in the IP Catalog. So how can I add it to my design? regards MikeRe: Problem with IP core Plus
Thank you, of course I have no license for the core. The distributor tells me that there is no 60 days evaluation license available for these cores. So we are back to the question why the open core works fine (see attachment) and when I change the device it is no longer working, although it is enabled and I get this warning Warning(18390): Intel FPGA IP Evaluation Mode (Simulation-Only) feature is turned on for all cores in the design. regards Mike
