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MSenk1's avatar
MSenk1
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4 years ago

Problem with Signal Tap Logic Analyzer

Hi, I'm using Quartus 21.2. When I use the signal tap logic analyser I get a crash. The FPGA works fine with the loaded content. But the logic analyser crashes with this message: Problem Deta...
RichardT_altera's avatar
RichardT_altera
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4 years ago

Hi @MSenk1

I haven't seen this internal error(IE) before. Could you help to share your design .qar file that could duplicate this error? As without duplication of the error from our side, it would be hard to find a workaround/solution.

* If your design is confidential, please help to create a simplified design that can duplicate the IE.

Please help to provide any specific steps on when this IE occurs, does it crash when you try to open the Signal Tap tool or running the tool ?

Please expect that any work involving engineering will take some-time (a few days to a few weeks) depending on the complexity of the issue.

If your project is urgent, I would recommend to use Quartus 21.1 as a temporary workaround.

Best Regards,
Richard Tan

MSenk1's avatar
MSenk1
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4 years ago

Hi Richard,

we were able to solve this issue internally.

Thanks

Michael

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi @MSenk1

    Glad to know that you are able to proceed without any trouble.

    Do you mind to share what you have done and how to resolve the error?

    This may be helpful to those who come across similar issue.


    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.