hbl
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Quartus License
Our license is locked to agilex5e which means we can only target Agilex5 FPGA (apart from Cyclone which doesn't require a license). We would like to target Agilex7 as well as other Altera FPGA families (Stratix and Arria). How can we generate a license that supports all of these FPGA families?716Views0likes2CommentsRe: Get available memory in an FPGA part using Tcl
What I am looking for is the total memory bits in a part, similar to what is reported when selecting a device in the Quartus gui (Assignmens -> Device...). I am not looking for resources usage, etc. tied to a specific project. Thanks1.3KViews0likes0CommentsRe: Adding SV interface to PD _hw.tcl
I think the SV interface support in PD that doesn't make any sense at all. For example, the "system verilog interface" option in PD is absolutely useless (cannot be edited in the GUI and if set in the _hw.tcl it doesn't show up in the GUI). Using USE_ALL_PORTS by itself doesn't work unless, I think, the port is added to the PD module somehow (can't figure out that one yet, I tried "add_interface_port bus_if data but" it didn't work due to undefined bus_if interface). If that's the case, might as well add the individual signal separately to the top module. Anyway, I think I wasted enough time on this useless option. Conclusion, unless someone can demonstrate a working example, SV interfaces are not supported in Platform Designer (Quartus Prime Pro).2KViews0likes0CommentsRe: Adding SV interface to PD _hw.tcl
Yes. This example (the only one we can find on Intel website) is very confusing; there are two interfaces (one avalon_slave and one SV interface) that have the exact same signal names! Adding just the SV interface part doesn't work (we keep getting the errors mentioned in my original post). We tried so many different combinations but nothing worked! My question is quite simple. What is the procedure to follow to define an SV interface in PD _hw.tcl file. For example: 1. add_sv_interface bus_if system_bus_if 2. set_sv_interface_property bus_if USE_ALL_PORTS True ... (what's missing here?) 4. set_port_property data SV_INTERFACE_SIGNAL bus_if2KViews0likes0CommentsAdding SV interface to PD _hw.tcl
Trying to define a SV interface in PlatformDesigner _hw.tcl file but I keep getting error message about port/interface! The SV interface declaration was loaded using: add_fileset_file system_bus_if.sv SYSTEM_VERILOG PATH system_bus_if.sv SYSTEMVERILOG_INTERFACE I've added the following to the _hw.tcl file add_sv_interface bus_if system_bus_if set_port_property data SV_INTERFACE_SIGNAL bus_if This triggered a "No port data" error. Then I added add_sv_interface bus_if system_bus_if add_interface_port bus_if data data Input 8 set_port_property data SV_INTERFACE_SIGNAL bus_if which triggered an "interface bus_if does not exist" error. What's the correct syntax to declare SV interface in PD _hw.tcl file? Thanks2.1KViews0likes10CommentsRe: MAX10 In-System Programming (ISP)
I don't agree with your conclusion! According to the doc that you've referenced, the CFM can be programmed by the core in real-time mode (bypassing the JTAG). Now, the doc (as well as the rest of references on MAX10) are not very clear for the case of a single compressed image. Can the image be updated in real-time remotely? Would it be possible to forward this question to a higher support level within Intel? Thanks1.6KViews0likes0CommentsMAX10 In-System Programming (ISP)
We are using a MAX10 FPGA with a single compressed image and would like to re-program the FPGA in the field using ISP. Intel documentation as well as the posts we came across on this forum talk about using JTAG. However, would it be possible to directly write to the internal CFM (configure as Read-Write) and reboot the FPGA? Does anyone have any hands-on experience with such an approach?1.7KViews0likes6Comments