Adding SV interface to PD _hw.tcl

Question

Trying to define a SV interface in PlatformDesigner _hw.tcl file but I keep getting error message about port/interface! The SV interface declaration was loaded using:

add_fileset_file system_bus_if.sv SYSTEM_VERILOG PATH system_bus_if.sv SYSTEMVERILOG_INTERFACE

I've added the following to the _hw.tcl file

add_sv_interface bus_if system_bus_if

set_port_property data SV_INTERFACE_SIGNAL bus_if

This triggered a "No port data" error. Then I added

add_sv_interface bus_if system_bus_if

add_interface_port bus_if data data Input 8

set_port_property data SV_INTERFACE_SIGNAL bus_if

which triggered an "interface bus_if does not exist" error.

What's the correct syntax to declare SV interface in PD _hw.tcl file?

Thanks

sstrell · Answer

Did you follow this: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/declaring-systemverilog-interfaces-in-hw-tcl.html

The signal should be readdata or writedata, not just "data", but make sure you follow the rest of the example in the user guide.

Also, I presume you are using Pro, not Standard.

hbl · Answer

Yes. This example (the only one we can find on Intel website) is very confusing; there are two interfaces (one avalon_slave and one SV interface) that have the exact same signal names! Adding just the SV interface part doesn't work (we keep getting the errors mentioned in my original post). We tried so many different combinations but nothing worked!

My question is quite simple. What is the procedure to follow to define an SV interface in PD _hw.tcl file. For example:

1. add_sv_interface bus_if system_bus_if

2. set_sv_interface_property bus_if USE_ALL_PORTS True

... (what's missing here?)

4. set_port_property data SV_INTERFACE_SIGNAL bus_if

sstrell · Answer

Did you try "readdata" or "writedata" instead of just "data"?  If you have no ports defined correctly in the interface, that might explain why you get the interface does not exist error.  There has to be at least one signal/port in an interface.

hbl · Answer

Not sure what you are referring to. The bus_if signal (not port) is called data (see below). How's this going to affect the SV definition?interface bus_iflogic [7:0] data;endinterface

sstrell · Answer

You have to use the standard signal names to define signal roles in an interface for a custom component.  A SystemVerilog interface is not exactly the same as a Platform Designer interface.  In the example, it shows 4 signals: address, write, writedata, and readdata.  These match the names that must be used for Avalon.  You can use different names in your code but then there must be a mapping to the correct signal roles for the Platform Designer interface using SV_INTERFACE_SIGNAL to add the signals to the interface and SV_INTERFACE_SIGNAL_NAME to do the name mapping: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/port-properties-38884.html.  With a SV interface, you can use the USE_ALL_PORTS property, but then the signal names in your SV interface must exactly match the signal roles defined in the spec: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.htmlI don’t know why USE_ALL_PORTS is in that example if the ports are then defined right there, but here’s the page describing USE_ALL_PORTS: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/systemverilog-interface-properties.html So the short and easiest answer is if your signal names in your SV interface match the required signal role names in the Avalon spec, you can just use USE_ALL_PORTS to set up the interface.

Forum Discussion

Adding SV interface to PD _hw.tcl

10 Replies

Recent Discussions

Arria 10: Remote Update Watchdog unpredicted behavior

Cyclone IV E(EP4CE30) FPGA JTAG and USB-Blaster

Agilex 5 BSDL Files

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

Agilex 7 R-Tile RBES FPGA – Board Fails to Power On and JTAG Not Detected