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hbl's avatar
hbl
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2 years ago

Adding SV interface to PD _hw.tcl

Trying to define a SV interface in PlatformDesigner _hw.tcl file but I keep getting error message about port/interface! The SV interface declaration was loaded using: add_fileset_file system_bus_if....
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sstrell's avatar
sstrell
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2 years ago

You have to use the standard signal names to define signal roles in an interface for a custom component. A SystemVerilog interface is not exactly the same as a Platform Designer interface. In the example, it shows 4 signals: address, write, writedata, and readdata. These match the names that must be used for Avalon. You can use different names in your code but then there must be a mapping to the correct signal roles for the Platform Designer interface using SV_INTERFACE_SIGNAL to add the signals to the interface and SV_INTERFACE_SIGNAL_NAME to do the name mapping: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/port-properties-38884.html. With a SV interface, you can use the USE_ALL_PORTS property, but then the signal names in your SV interface must exactly match the signal roles defined in the spec: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.html

I don’t know why USE_ALL_PORTS is in that example if the ports are then defined right there, but here’s the page describing USE_ALL_PORTS: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/systemverilog-interface-properties.html
So the short and easiest answer is if your signal names in your SV interface match the required signal role names in the Avalon spec, you can just use USE_ALL_PORTS to set up the interface.
hbl's avatar
hbl
Icon for New Contributor rankNew Contributor
2 years ago

I think the SV interface support in PD that doesn't make any sense at all. For example, the "system verilog interface" option in PD is absolutely useless (cannot be edited in the GUI and if set in the _hw.tcl it doesn't show up in the GUI).

Using USE_ALL_PORTS by itself doesn't work unless, I think, the port is added to the PD module somehow (can't figure out that one yet, I tried "add_interface_port bus_if data but" it didn't work due to undefined bus_if interface). If that's the case, might as well add the individual signal separately to the top module.

Anyway, I think I wasted enough time on this useless option. Conclusion, unless someone can demonstrate a working example, SV interfaces are not supported in Platform Designer (Quartus Prime Pro).

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