New Contributor
Super ContributorDid you follow this: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/declaring-systemverilog-interfaces-in-hw-tcl.html
The signal should be readdata or writedata, not just "data", but make sure you follow the rest of the example in the user guide.
Also, I presume you are using Pro, not Standard.
New ContributorYes. This example (the only one we can find on Intel website) is very confusing; there are two interfaces (one avalon_slave and one SV interface) that have the exact same signal names! Adding just the SV interface part doesn't work (we keep getting the errors mentioned in my original post). We tried so many different combinations but nothing worked!
My question is quite simple. What is the procedure to follow to define an SV interface in PD _hw.tcl file. For example:
1. add_sv_interface bus_if system_bus_if
2. set_sv_interface_property bus_if USE_ALL_PORTS True
... (what's missing here?)
4. set_port_property data SV_INTERFACE_SIGNAL bus_if
