Mathiazhagan
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Re: Auto increment address in the memory in a verilog program
Dear Ean, No, I did not get any update for this problem, I have tried but i could not solve the problem, could u please share me a sample code for the above mentioned problem, which will be very much useful for me to proceed further. Awaiting for your favorable response. With Regards, V.MathiazhaganRe: Auto increment address in the memory in a verilog program
Dear Sir/Madam, Yes as you mentioned the addr[ADR-1:0] has been assigned as input, but the input cannot be declared as a register right, then how to solve the issue. On a condition @ every posedge clk my address should get auto incremented and in that auto incremented address i have to store some value. If possible could u please share me a code for this ,Which will be very much useful for me to proceed further. With Regards, V.MathiazhaganAuto increment address in the memory in a verilog program
Hi there, Am a new learner in verilog, So please help me out how to resolve this issue I have created a simple SRAM Module I want to increment my address on posedge of every clock pulse, but i don't know how to do it, so anyone please help me out in resolving this issue I have posted my verilog code too module sramw(dataIn,dataOut,Addr,CE,WE,OE,RD,Clk,RST,//count ); parameter ADR = 19; parameter DAT = 8; parameter DPTH = 524288; //parameter COUNT = 19; input [DAT-1:0] dataIn; output reg [DAT-1:0] dataOut; input [ADR-1:0] Addr; input CE, WE, RD, Clk, RST, OE; //reg Addr //internal variables reg [DAT-1:0] SRAM [DPTH-1:0]; always @ (posedge Clk) begin if (CE == 1'b0) begin if (WE == 1'b0 && RD == 1'b0) begin SRAM [Addr] = dataIn; end else if (RD == 1'b1 && WE == 1'b1) begin dataOut = SRAM [Addr]; end else; end else; end endmodule
