Forum Discussion
Porting from Xilinx to Altera
- 4 years ago
I believe I have provided the support/answer that you needed in order to proceed with your project. With that, this thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
When I try to convert the project, the tool error out that below file is missing. Please kindly check and ensure that the files is provided.
../Hexa_Rex_2.1_HD_V1.1/Hexa_Rex_2.1_HD_V1.1.srcs/sources_1/new/HD_SORTER/calib_Bram_IF.v doesn't exist in the Xilinx project directory.
Try to compile the design with the attachment that you provided. If it can't, probably means there is something wrong.
Best Regards,
Richard Tan
Dear Richard Tan,
I have once again shared you the project files via ftp. Kindly look into it and let me know if you have any issues regarding the file shared. The file shared is the compiled one, Which is synthesized at my end in vivado 2015.4 version without any runtime error.
With Regards,
V.Mathiazhagan