Auto increment address in the memory in a verilog program

Hi there,

Am a new learner in verilog, So please help me out how to resolve this issue

I have created a simple SRAM Module

I want to increment my address on posedge of every clock pulse, but i don't know how to do it, so anyone please help me out in resolving this issue

I have posted my verilog code too

module sramw(dataIn,dataOut,Addr,CE,WE,OE,RD,Clk,RST,//count
);
parameter ADR = 19;
parameter DAT = 8;
parameter DPTH = 524288;
//parameter COUNT = 19;
input [DAT-1:0] dataIn;
output reg [DAT-1:0] dataOut;
input [ADR-1:0] Addr;

input CE,
WE,
RD,
Clk,
RST,
OE;
//reg Addr
//internal variables
reg [DAT-1:0] SRAM [DPTH-1:0];
always @ (posedge Clk)
begin
if (CE == 1'b0) begin
if (WE == 1'b0 && RD == 1'b0) begin
SRAM [Addr] = dataIn;
end
else if (RD == 1'b1 && WE == 1'b1) begin
dataOut = SRAM [Addr];
end
else;
end
else;
end
endmodule