lingxi10
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Re: HLS compiler failed
Hi, Sorry for the late reply. My email is not giving me proper notifications for the update. Sorry can you elabrate more on how to use sizeof? I didn't find much information from the link you provided. This is the struct I used for the streaming interface: struct samples { hls_register ac_int<DATAWIDTH, true> data[NCHAN]; hls_register float currSum; }; using namespace ihc; typedef ihc::stream_in<samples, ihc::usesReady<false>, ihc::usesValid<false>> sampleStream_t; I think I already defined the size of the streaming input in the struct?Re: HLS compiler failed
Hi there, Thanks for replying. The input type is ihc::stream_in<samples, ihc::usesReady<false>, ihc::usesValid<false>> where samples is an input with 4096 bits. I ran HLS compiler using i++ command and according to the debug.log I attached in my previous post, the process seems to failed at generating qsys interface for the component Here is what I did and the info printed in the terminal if that help: Command: i++ -march=Stratix10 -ghdl SumAndSquare.cpp -o SumAndSquare Result: HLS Generate testbench QSYS system FAILED. See **/debug.log for details. make: *** [<builtin>: SumAndSquare] Error 1Configuring Native PHY IP for QSFP transceiver
Hi there, We are trying to configure a transceiver on a stratix 10 device. The transmitter and receiver are on same board. The 50Mhz global clock goes through an IOPLL IP core to create 100Mhz clock for user logic, input clock of the reset controller for both transmitter and receiver, and the input clock for the reference clock of the receiver. Reference clock of the transmitter is the clock pin on QSPF28 Ports, which is 644.53125Mhz. It goes through fPLL IP core of the transceiver and create 500Mhz output clock as indicated by the Native PHY IP core for transceiver with 1000Mbps datarate. Now the simulation is working, and we tested the transmitting side using oscilloscope. It seems that the data from the transmitting side is doing correctly. But on the receiver side, the patterndetect signal never goes high and the parallel data cannot be recevied. Below attached the project. I am wondering if some configurations are wrong or we are missing something? Thanks for the help! Update: I also attached the simulation screenshot here. The serial data transmitted from the transmitter core is going directly into the receiver core. There are glitches on the data line though. Not sure if anyone has the same problem?Intel FIFO behave differently for M20K and MLAB memory configuration
Hi there, I am building a project that uses DCFIFO. The write clock comes from PCIe with 125MHz and the read clock comes from PLL with 180MHz. The problem is when I am configuring the FIFO with M20K memory type, the very first data is unstable, meaning sometimes it gives the output of the second data and sometimes it gives the right output. The simulation is correct but the data in the physical board Stratix 10 is wrong. I used signal tap to go down to the writing and reading pointer of the FIFO and also the writing and reading data. The writing data is right but the reading data give the wrong result. However this doesn't happen why I instead use the MLAB memory to configure it. For the timing constraint, I selected the "Generate SDC file and disable embedded timing constraint" to let the tool generate it automatically. Can someone help? Thank you so much!Re: License server does not support this feature (alteramtivlog)
Here is how I setup my license: export LM_LICENSE_FILE="/home/shirley/1-U8XDY3_License.dat" export MGLS_LICENSE_FILE="/home/shirley/1-U8XDY3_License.dat" where the dat file is my license file. I was able to use the same license file for Quartus. For firewall, this licence is specifically generated for the IP address of this computer and I was able to use Quartus just fine so I don't understand why modelsim doesn't work. Below attach the beginning of the license. I think one thing bothers me is in the comment that the expiration data is the same day that I applied for this license. Not sure if this may cause problem?License server does not support this feature (alteramtivlog)
odelsim license not working, GUI can be open up and vlog is fine. When starting the stimulation, it gives to following issue: # vsim work.tb # Start time: 12:38:49 on Jun 23,2021 # # ** License Issue: License server does not support this feature (alteramtivlog) # ** License Issue: No such feature exists. (/home/shirley/1-U8XDY3_License.dat) # ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: 'alteramtivsim' or 'alteramtivlog'. # Error loading design # End time: 12:38:50 on Jun 23,2021, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Anyone has any idea why this happens? Thanks a lot!
