Hi there,
Thanks for replying. The input type is ihc::stream_in<samples, ihc::usesReady<false>, ihc::usesValid<false>> where samples is an input with 4096 bits. I ran HLS compiler using i++ command and according to the debug.log I attached in my previous post, the process seems to failed at generating qsys interface for the component
Here is what I did and the info printed in the terminal if that help:
Command: i++ -march=Stratix10 -ghdl SumAndSquare.cpp -o SumAndSquare
Result: HLS Generate testbench QSYS system FAILED.
See **/debug.log for details.
make: *** [<builtin>: SumAndSquare] Error 1