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lingxi10's avatar
lingxi10
Icon for New Contributor rankNew Contributor
4 years ago

Intel FIFO behave differently for M20K and MLAB memory configuration

Hi there, I am building a project that uses DCFIFO. The write clock comes from PCIe with 125MHz and the read clock comes from PLL with 180MHz. The problem is when I am configuring the FIFO with M2...
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,

It is recommended for you is to use FIFO IP core generated from Quartus GUI (not from Platform Designer).
Then you can see the generated sdc file for the FIFO IP core and based on the file create your own SDC file for your custom-atom FIFO instances. Please aware that different configuration of FIFO may generate different SDC file.

regards,

Farabi

lingxi10's avatar
lingxi10
Icon for New Contributor rankNew Contributor
4 years ago

I am using the FIFO IP core generated from Quartus GUI. This problem was fixed by selecting the setting to make the aclr of fifo to be synchronized to both read clk and write clk. Thanks for the help