burakduysak
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Video Stream over ethernet
I am fresh new at ethernet communications. I have some questions about it. Can I send my camera stream(640x480) to pc over ethernet? How is that possible? Can I use VIP cores for it? As I said I am fresh new at Ethernet protocols, Where should I start to learn?853Views0likes1CommentVIP Suite Design Example
I am trying to implement the VIP Design Example "https://www.intel.com/content/www/us/en/programmable/products/reference-designs/all-reference-designs/broadcast/ref-post-processing.html" I have a DE2-115 board and I have one composite input (PAL configuration). My output is 640x480 VGA. I managed to work with CVO II core and its works fine, after that I connected 3 TPG and "1 composite input path" to Mixer II core.Each TPG at 320x240 and I scaled the composite video to 320x240 as well. 1-My Frame Buffer and Deinterlacer cores use SDRAM as external memory.Is that a problem ? 2-My composite input is not stable,I can see there is a real capture but its flickering too much. When I checked "CVI.is_valid_resolution()" ,I got false as return value.Why is that happen ? My Composite Video path CVI II(8 bits,2 color planes,Sequence,Any field first,Embedded in video,Interlaced,720 288 288 , 1024 FIFO size) => CLIPPER II (RECTANGLE 720 240 ,3 Top offset) => Color Plane Sequencer II(8 2 1 sequence, 8 2 1 parallel) => Chorama Resampler II (Horizontal NEAREST NEIGHBOUR , Vertical NEAREST NEIGHBOUR,Enable 4:2:2 Input, Enable 4:4:4 Output)=>Color Space Converter II (Input bits per color space 8,Output bits per color space 😎 => Deinterlacer II (Motion adaptive ,produce one frame for every field,Avalon MM local ports width 32 ) =>Scaler (320X240 as output and algorithm is Nearest Neighbour) => Framebuffer II(Avalon MM local ports width 32 No frame repeating or dropping)=>Mixer II (No Alpha blending) =>CVO Any would be appreciated2.1KViews0likes2CommentsRe: fatal error: cstdarg: No such file or directory
I solved the issue. I think this is an eclipse IDE issue. I add 2 more paths to Application Include Directories, which is under Properties>Nios 2 Application Properties>Nios 2 Application Paths, then change my main. c to main.cpp I attached the paths.5.2KViews0likes1Commentfatal error: cstdarg: No such file or directory
I was trying to implement Video and Image Processing Design Example (https://www.intel.com/content/dam/altera-www/global/en_US/uploads/2/2a/Video_and_Image_Processing_Design_Example_16_1.pdf) but for only one composite video input.When I try to include .hpp files to my nios2 main.c, I got following error : 15:43:49 **** Incremental Build of configuration Nios II for project vip_system **** wsl make all Info: Building /mnt/d/FPGA/VIP_CORE/software/vip_system_bsp/ make --no-print-directory -C /mnt/d/FPGA/VIP_CORE/software/vip_system_bsp/ [BSP build complete] Info: Compiling hello_world.c to obj/default/hello_world.o nios2-elf-gcc.exe -xc -MP -MMD -c -Id:/FPGA/VIP_CORE/software/vip_system_bsp//drivers/vip/../../drivers/vip/inc -Id:/FPGA/VIP_CORE/software/vip_system_bsp//drivers/vip/../../drivers/vip/src -Id:/FPGA/VIP_CORE/software/vip_system_bsp//HAL/inc -Id:/FPGA/VIP_CORE/software/vip_system_bsp/ -Id:/FPGA/VIP_CORE/software/vip_system_bsp//drivers/inc -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -mno-hw-div -mno-hw-mul -mno-hw-mulx -mgpopt=global -o obj/default/hello_world.o hello_world.c In file included from d:\fpga\vip_core\software\vip_system_bsp\drivers\vip\inc\VipCore.hpp:4, from d:\fpga\vip_core\software\vip_system_bsp\drivers\vip\inc\clipper.hpp:4, from hello_world.c:18: d:\fpga\vip_core\software\vip_system_bsp\drivers\vip\inc\VipUtil.hpp:13:10: fatal error: cstdarg: No such file or directory #include <cstdarg> ^~~~~~~~~ Makefile:724: recipe for target 'obj/default/hello_world.o' failed compilation terminated. make: *** [obj/default/hello_world.o] Error 1 What could be the reason ?Solved5.3KViews0likes2CommentsWrite Avalon-ST data packets to sdram
I am wondering that how can I write the Avalon-st data packets to SDRAM (which is use Avalon mm interface) without using Nios II. Should I use Avalon FIFO Memory as input side AVALONST_SINK and output side AVALONMM_READ. And for reading to SDRAM I need to do Avalon MM to Avalon ST conversion as well. Thanks for any help.703Views0likes1CommentRe: Camera Application on DE2-115
Thanks for your reply , Before implementing that project I tried it that manually, I mean I manually wrote some data into SDRAM then write it to DC FIFO from sdram and read these data from reading side of the DC FIFO. The writing side was 143 Mhz and the reading side was 108 Mhz, I got clear colors on VGA display. I ensure it like that. I hope that was enough.Today I tried to implement video-in example from (ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/14.0/University_Program_IP_Cores/Audio_Video/Video.pdf) which is pdf that you shared. But I didn't use Nios II softcore processor, am I have to use it ? I am getting white screen nothing else. Can I do it without Nios II ? Here is my design.3.3KViews0likes0CommentsCamera Application on DE2-115
Hello everyone, I want to implement a camera application on the Altera DE2-115 board. I aim to get four different camera output on one screen, here is a very similar project:https://youtu.be/RlrAdS8eaxc, instead of this one I am using an analog camera (CCD PAL). For now, I try to get only one camera output on the VGA monitor. I am using these IP cores for this project: Video-in decoder Audio Video Config Chroma Resampler Color-space converter (422 to 444) 2x DUAL CLOCK FIFO SDRAM CONTROLLER Intel FPGA IP I couldn't get any data from my fifo_out_data signal. Also I am wondering that how can I write avolon package signal into the avalon MM slave which is rgb to sdram in my project. And same for vice versa which is sdram to fifo_in in my project. Am I have to deal with crossing clock domain ? , because I am using dual clock fifos I think I don't need to. I attached my project file. Thanks for any help..Solved3.3KViews0likes4Comments