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PShar32
Occasional ContributorJoined 6 years ago
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Re: Multiple NIOS V Implementation
I am thinking of : Compile the niosV codes in ashling. Generate .hex files for all the nios V processors. in platform designer , initialize the on-chip memory of NiosV with the hex file. Compile the Qsys. Compile the Quartus project. Dump the .sof file. Will this work,.. ?39Views0likes2CommentsRe: Nios II, floating point hardware.
Thankyou for the reply, As I understand, you are suggesting me as i don't need anything else to perform high speed 64 bit multiplication as NIOS II/f already has hardware multipliers and extended multipliers/ But I can further improve the speed if my multiplication variables does not depend upon previous operation. right ? Pratik2.1KViews0likes0CommentsRe: Nios II, floating point hardware.
Hello, thank you, for your reply, also the link you suggests to make multiplication in assembly code. I am writing in c++, how will I write those functions ? (Mul r1, r2, r3)?? Is there any other means to make the “ 64 bit double precision “ multiplication more faster, in nios II. .? //2.1KViews0likes0CommentsNios II, floating point hardware.
Hi, Hi, I want to perform some huge multiplications in nios 2 processor, I learned that unlike ‘nios 2 e’ , nios 2 fast says it does hardware based multiplication, so adding floating point hardware is worthless or it will further reduce computation time ?Solved2.2KViews0likes6CommentsRe: Quartus Prime Lite with NIOS2 Generates Time Limited SOF File
I Think it doesn't matter I have a license for NIOS II IP core. When I use only NIOS II fast core it does not give any error. I might need a Licensed version of Quartus Prime software (standard version) getting rid of that king of error. and be able to generate general .sof file (not time_limited .sof file). regards --------- Pratik Sharma4.3KViews0likes0Commentslicense for quartus.
Hi. I am developing in a cyclone V FPGA and my design uses NiosII and HPS in. I am able to successfully verify the design and working properly using Quartus prime Lite. but it runs in evaluation mode (I have to keep my device tethered). I think I should buy license for Quartus prime standard version for deploying my complete system hardware in feild. How/and where to get such License..? will i be able to use nios2 fast core IP...? and will the license is for lifetime ..? regards ------- PratikSolved1.2KViews0likes3CommentsRe: not able to detect any instance for core < hps_sdram_p0 >
hi,.. I was suffering the same .. and I followed the steps you provided.. and when I run TCL scrip I get error like. Error:Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper) Error:Error: The core is not the top-level of the project Error:Error: The memory interface pins are exported to the top-level of the project Error:Error: Alternatively, if you are no longer instantiating core < hps_sdram_p0 >, Error:Error: clean up any stale SDC_FILE references from the QSF/QIP files. Error:Info: Dumping reference pin-map file: hps_sdram_p0_all_pins.txt Error:Error (23031): Evaluation of Tcl script F:/<----->/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl unsuccessful Error:Error: Quartus Prime TimeQuest Timing Analyzer was unsuccessful. 8 errors, 3 warnings. But when I delete the <hps_dram_p0.sdc> from /synthesis/submodules I see no error in main compiler..... ! but it shows some error when i use nios II fast core.. like Error (210039): File F:/micro_pmu_structure_01/output_files/micro_pmu_daq_time_limited.sof contains one or more time-limited megafunctions that support the Intel FPGA IP Evaluation Mode feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.2.3KViews0likes0Comments