Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Agilex 7 FPGA Starter Kit with oneAPI Toolkit flow not detected over PCIe
Hello, I’m trying to use a Terasic Agilex 7 FPGA Starter Kit (A7SK, rev.A) with the Intel oneAPI toolkit, following Terasic’s official A7SK oneAPI manual. The ASP image appears to load successfully, but after reboot the host does not detect the board as a PCIe device. The system behaves as if no PCIe card were present. The board is powered correctly, SW4 is set for x8, and the USB/JTAG side is visible, but the PCIe endpoint never enumerates. Has anyone here successfully made the Terasic A7SK work with oneAPI? Has anyone seen a similar issue where the board never appears over PCIe after reboot? Any experience, confirmation, or suggestions would be very helpful. Thanks.
MCTP over PCIe VDM routing to PMCI in OFS N6000 FIM configuration and datapath clarification
Hi Team, I am working on implementing PLDM over MCTP over PCIe VDM on the Intel N6000 platform OFS PCIe Attach FIM. I have referred the following documents: 1. OFS Linux MCTP driver documentation: https://github.com/OFS/linux-dfl/blob/2014c95afecee3e76ca4a56956a936e23283f05b/Documentation/networking/mctp.rst 2. OFS Agilex PCIe Attach FIM architecture guide: https://ofs.github.io/ofs-2025.1-1/hw/n6001/dev_guides/fim_dev/ug_dev_fim_ofs_n6001/#1211-top-level From my understanding, the PMCI module inside the FIM contains the MCTP over VDM controller which transmits MCTP payloads containing PLDM commands to the MAX10 BMC. The BMC communicates with PMCI via SPI. The host can access PMCI CSRs through PCIe MMIO and this is working in our setup using the intel-m10-bmc driver. However, the datapath for MCTP over PCIe VDM from the host is unclear. I have the following questions: 1. How are PCIe VDM packets generated from the host routed to the PMCI MCTP controller inside the FIM? 2. Is there any specific configuration or enablement required in the PCIe subsystem or FIM fabric to allow VDM packets to reach PMCI? 3. What is the role of the MCTP Management Interface or MCTP VDM controller IP in the OFS FIM design? 4. Is this a custom IP responsible for filtering or routing VDM packets? How is this block exposed to the host? 5. Are there any registers, BAR mappings, or configuration steps required to enable this datapath? Does the Linux MCTP stack directly interact with PMCI, or is routing handled entirely in hardware? Currently, we are able to generate PCIe VDM packets from the host, but they are not observed at the PMCI or BMC side. This suggests that the ingress path may not be enabled or packets are being filtered before reaching PMCI. Any clarification on the expected datapath and required configuration for enabling host to PCIe VDM to PMCI to BMC communication would be very helpful. Thanks and regards, Nafiah Siddiqha
Agilex 7 M series Open FPGA Stack support
Hello, We are using Agilex 7 M series FPGA and considering to evaluate Open FPGA Stack (OFS) at some point. Currently the latest OFS release (2025.1) contains only pre-release level support for Agilex 7 M reference shell design and lacks support for many key features (https://github.com/OFS/ofs-agx7-pcie-attach/releases/tag/ofs-2025.1-1). Could we expect to get an official release level support some time in the near future? Best regards OttoUnderstanding FPGA AI Suite with Quartus
Hi, I am new to the FPGA AI Suite and would appreciate your help in better understanding it. Referring to the attached Intel pipeline, specifically the path involving Quartus: When Quartus is involved, is the OpenVINO runtime inference engine still required to run the application? I assume that IP files are imported into Quartus. Do these files contain the model topology and weights needed to run the application, or is Quartus solely used to configure the FPGA hardware, with the inference handled by the OpenVINO runtime (via FPGA AI Suite)? If I test the model using a deep learning framework and then use the FPGA AI Suite, how can I effectively collaborate with the FPGA developer? I hope my questions are clear. Best regards.Intel FPGA AI Sutie Inference Engine
Is there any official documentation on the DLA runtime or inference engine for managing the DLA from the ARM side? I need to develop a custom application for running inference, but so far, I’ve only found the dla_benchmark (main.cpp) and streaming_inference_app.cpp example files. There should be some documentation covering the SDK. The only documentation that i found related with is the Intel FPGA AI suite PCIe based design example https://www.intel.com/content/www/us/en/docs/programmable/768977/2024-3/fpga-runtime-plugin.html From what I understand, the general inference workflow involves the following steps: Identify the hardware architecture Deploy the model Prepare the input data Send inference requests to the DLA Retrieve the output data
OFS : Data Path of QSFP from HE_HSSI
Hi Team, I am using N6001 with Intel OFS (OFS PCIe Attach) . I wanted to test data transfer from Host1 to Host2 as below. Host1 -> N6001(Port0) -> OtherNIC(Port0) -> Host2. Is there any sample application available in OPAE/OFS which performs this transaction? Can you please suggest. In addition to above query, I wants to know how HE-HSSI sends data to QSFP?. The hssi application shows "No eth interface, so not honoring --eth-loopback". ( https://ofs.github.io/ofs-2024.1-1/hw/n6001/user_guides/ug_qs_ofs_n6001/ug_qs_ofs_n6001/ Section 7. Send traffic through the 10G AFU). Does this mean the HE_HSSI will not communicate with E-Tile or QSFPs (FIM) ? Do I need to enable any parameters to pass over QSFPs? Thankyou.
Issue with Compiling OFS Agilex PCIe Attach on F-Series Development Kit
Hello Team, I am looking to compile the OFS Agilex PCIe Attach on the F-series development kit. I was following the compilation flow using the link below: https://ofs.github.io/ofs-2023.3/hw/ftile_devkit/dev_guides/fim_dev/ug_ofs_ftile_dk_fim_dev/#1311-walkthrough-install-quartus-prime-pro-software After exporting with the respective Quartus and build root, I am facing an issue where the terminal hangs. and the compilation doesn't go any further for hours. I have compiled this on both Red Hat Enterprise Linux 8.6 and Ubuntu 22.04 having same observation. I am using a system with an Intel i7-14700 and 64GB of RAM, so system performance shouldn't be an issue. I have also attached logs for your reference. Kindly provide a solution or let me know if any changes need to be made. Thanks & Regards, RaizzHow to Reconfigure and make changes in Quartus for a built and compiled OFS FIM.
Hello, I have built and compiled the N6001 design from otchsare beta 3.2 SKU2 version using Quartus 23.1. It seems that within the FIM developer documents the steps to reconfigure and change the design are given all via the terminal and using Quartus commands. I was wondering if I can do design changes and other stuff within Quartus and give compilation from within quartus after building the design once. So when I tried compiling the same design without any changes from within Quartus, there were multiple tcl files which were throwing errors. -------------------------------------------------------------------------------------------------- Tcl error: can't find package options while executing "package require options" (file "ofs_partial_reconfig/user_clock_freqs_compute.tcl" line 24) invoked from within "source ofs_partial_reconfig/user_clock_freqs_compute.tcl" (file "ofs_partial_reconfig/ofs_sta_report_script_pr.tcl" line 12) invoked from within "source ofs_partial_reconfig/ofs_sta_report_script_pr.tcl" ("uplevel" body line 1) invoked from within "uplevel source $script" invoked from within "if [file exists $script] { set start_time [clock clicks -millisec] uplevel source $script set end_time [clock clicks -millisec]..." ("foreach" body line 2) invoked from within "foreach script $options(report_script) { if [file exists $script] { set start_time [clock clicks -millisec] uplevel source $scri..." invoked from within "if [is_project_open] { # The all_corners option can be set by INI as well. set all_corners_ini [get_ini_var -name "qsta_all_corners"] if {[stri..." (procedure "main" line 140) invoked from within "main" (file "t:/intelfpga_pro/23.1/quartus/common/tcl/internal/qsta_default_script.tcl" line 1610) ------------------------------------------------------------------------------------------------------- So I went through the document again and found out about Relocatable PR Directory. And I thought this is used to create a project which can be used to compile within quartus. So I tried running this and got it to work successfully, but I think I must've misunderstood what this means since it doesn't generate a Complete Quartus project file with every file present within the Quartus Project, but generates some files and binaries. What exactly is this feature used for? Is there any way after building the Quartus project in the Linux environment, after which I can copy the project file and then continue designing in a Windows environment without having to run scripts and just use Quartus to do everything?
