Why can’t I place the bytes of two LVDS SERDES IP instances (in TX or Non-DPA RX modes) to the same IO sub-bank on Agilex™ 5 in Quartus® Prime Pro Edition Design Software versions prior to 25.3?
Description Due to a problem in Quartus® Prime Pro Edition Design Software versions prior to 25.3, placing both LVDS SERDES IP instances within the same IO sub-bank may not be successful. If you attempt to put the bytes of both IP instances in the same IO sub-bank, you may encounter the following fitter error: Error(14996): The Fitter failed to find a legal placement for all periphery components. Resolution This problem has been fixed in the Quartus® Prime Pro Edition Design Software Version 25.3. Use the Quartus Prime Pro Edition Design Software Version 25.3 to generate the LVDS SERDES IP and compile the project. If you must use the Quartus Prime Pro Edition Design Software versions prior to 25.3, please contact Support with this KDB link. Related Articles Can I distribute the channels of an Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode between two sub-banks? How many IOPLLs are used when implementing Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO/Soft-CDR mode and distributing the channels between two sub-banks?
Why does the Nios® V/g processor return inaccurate floating-point calculation results when the Floating-Point Unit is enabled?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1, the Nios® V/g processor might return inaccurate floating-point calculation results when the Floating-Point Unit (FPU) is enabled. This problem is found in MAX® 10 FPGA devices only. Other Altera® FPGA devices are not affected. This is because there is a problem in the FPU module, which generates spurious signals affecting the calculation results. Resolution A patch is available to fix this problem for the Quartus® Prime Standard Edition Software version 24.1. Download and install patch 0.03 from the following links: Quartus® Prime Standard Edition Software v24.1 Patch 0.03 The problem has been fixed starting with Quartus® Prime Standard Edition software version 25.3.How do I install Cygwin for SoCEDS?
Description Starting with Quartus® Prime Standard and Pro Edition Software version 19.1 for Windows® and the Altera® SoC FPGA Embedded Development Suite (SoC EDS) version 19.1 for Windows, the Cygwin component must be installed manually. Administrative privileges are needed on the PC to perform the Cygwin installation. Resolution The procedure for installing Cygwin is as follows: Go to the official Cygwin website https://cygwin.com/ Download the 64bit installer (setup-x86_64.exe) Open a Windows Command Prompt Locate the path where Cygwin will be installed. For SoC EDS, the default path is C:\intelFPGA_pro\<version>1\embedded\host_tools\cygwin Run the installer in the Command Prompt with the following parameters (replace <<Path Cygwin Installer>> with the correct path): setup-x86_64.exe --wait --quiet-mode --root <<<Path Cygwin installer>> --site http://cygwin.mirrors.hoobly.com --packages make,gcc-core,gcc-g ,ncurses,inetutils,openssh,mosh,patch,flex,bison,tar,bzip2,zip,unzip,util-linux,git,subversion,vim,xxd,m4,wget,dos2unix,libintl devel,diffutils,libncurses-devel,iperf,xorg-server,xinit,mingw64-x86_64-gcc-core,mingw64-x86_64-gcc-g Make sure the command is all on a single line. Copying and pasting from this document may split the command into multiple lines. Press Enter to issue the command and wait until everything is automatically installed.How can I migrate my Nios II processor design to the Nios II Gen 2 processor?
Description The Nios ® II Gen 2 processor is introduced in the Quartus ® II software version 14.0. A migration script is provided for users to migrate from the Nios II processor to the Nios II Gen 2 processor. Resolution To migrate your existing Qsys design to the Nios II Gen 2 processor, follow these steps: Download “nios2_gen2_migration.tcl" and put the script in your project directory Run Nios II Command Shell in Window system or Console in Linux System Browse to your project directory and run below command: qsys-script --script= nios2_gen2_migration.tcl --system-file=<qsys_file>.qsys Regenerate Qsys and recompile your project after appling the TCL script in Quartus II and run “generate bsp-editor” in Nios II EDS. Related Articles How can I migrate the Nios II processor /s core to an equivalent Nios II Gen 2 processor /f core ?Why Nios II Sof2flash failed to generate flash file for Cyclone II?
Description Due to a problem in the Quartus® II software version 12.1SP1, the NIOS® II sof2flash utility is not able to generate a flash file from a Cyclone® II .SOF file. Resolution A patch is available to fix this problem for the Quartus II software version 12.1SP1. You must either have previously installed the Quartus II 12.1 SP1 software or must install the Quartus II 12.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly. Download and install the appropriate patch from the links below, then re-runthe sof2flash for Cyclone II design. Download quartusii-12.1sp1-1.72-windows.exe Download quartusii-12.1sp1-1.72-linux.tar Download quartusii-12.1sp1-1.72-readme.txt This problem is fixed for the Quartus® II software version 13.0 and later.Why do I see transceiver PMA functionality problems when using NIOS II as an Avalon Memory Mapped Master for the transceiver reconfiguration controller when using Stratix V, Arria V, or Cyclone V transceiver devices?
Description Due to a bug in the Quartus® II software version 13.0 and earlier, you may see transceiver PMA functionality problems when using NIOS II as an Avalon Memory Mapped Master for the reconfiguration controller when using Stratix® V, Arria® V, or Cyclone® V transceiver devices. When accessing the following transceiver PMA functions through the reconfiguration controller Avalon memory mapped interface using a NIOS II master or other Avalon master you may encounter a failure in the transceiver PMA. Stratix V GX/GT/GS, Arria V GZ Arria V GX/GT/ST/SX Cyclone V GX/GT/ST Pre and post CDR reverse serial loopback Pre and post CDR reverse serial loopback Pre and post CDR reverse serial loopback - Rx equalization Rx equalization The PMA failure is caused by corruption inside the reconfiguration controller if the reconfig_mgmt_address bus toggles when the reconfig_busy signal is asserted. The failure can be recovered by reprogramming the FPGA. Resolution To work around the problem, you can insert logic that prevents toggling of the reconfiguration controller reconfig_mgmt_address bus when the reconfig_busy signal is asserted. Or you can replace the "alt_xreconf_uif.sv" file that resides in your Reconfiguration Controller Megawizard™ generated <instance_name> folder with this file and recompile your design. This problem will be fixed in a future version of the Quartus II software.Why does Nios® II Software Build Tools for Eclipse hang when you try to run a project as Nios® II hardware ?
Description In the Quartus® II software version 10.1, the Nios® II Software Build Tools for Eclipse sometimes become unresponsive when you try to run (or debug) a project with the Run as Nios II Hardware (or Debug as Nios II Hardware) command. Resolution A patch is available to fix this problem for the Quartus II software version 10.1. Download and install the appropriate patch and readme file from the following links: Quartus II software version 10.1 patch 0.18 for PC (.exe file) Quartus II software version 10.1 patch 0.18 for Linux (.tar file) Quartus II software version 10.1 patch 0.18 readme.txt file This issue is scheduled to be fixed in a future release of the Quartus II software.Where is the GNU documentation for Quartus 13.0 and 13.1
Description Due to a problem in the Quartus® II software version 13.0 and 13.1, GNU documentation may not be present in the /nios2eds/documents/gnu-tools folder. Resolution To workaround this problem the documents can be downloaded from the following link: nios2eds_documents_gnu-tools.tar.gz (.tar.gz) This problem is scheduled to be fixed in a future release of the Quartus II software.Why does the Nios® V processor fail to generate HDL and report "Error: add_fileset_file" in the Quartus® Prime Standard Edition Software?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This problem is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl calls add_fileset_file on a simulator, which is not supported in Windows OS. The simulators are Cadence Simulator, Synopsys VCS*, and VCS MX. For information on the simulators' supported platforms, refer to Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators. Resolution To work around this problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, follow these steps: Navigate to the following hw.tcl files: <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_dbg_mod_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_timer_msip_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_g/intel_niosv_g_unit_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_m/intel_niosv_m_unit_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_c/intel_niosv_c_unit_hw.tcl Inside each hw.tcl file, find set simulators [list ]. Modify the subsequent if-else statement to, set simulators [list ] if {$sim_synth == "sim" } { if { [file exists intelfpga] && [file isdirectory intelfpga] } { set simulators [list intelfpga] } elseif { $::tcl_platform(platform) == "windows" } { set simulators [list aldec mentor] } else { set simulators [list aldec cadence mentor synopsys] } } The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1 and Quartus® Prime Standard Edition software version 25.1.Why does the Nios® V processor fail to generate HDL with an add_fileset_file error message in Quartus® Prime Standard Edition from Windows* OS?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This issue is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl is calling add_fileset_file on an unsupported simulator. These unsupported simulators are referring to simulators that are not supported in Windows* OS - Cadence Simulator and Synopsys VCS* and VCS MX. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patches below. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1 and Quartus® Prime Standard Edition software version 25.1. Additional Information For information on the simulators’ supported platforms, refer to the Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators.