add_instance: Component intel_niosv_m_unit version <x.y> is not installed - loaded latest installed version <x.y> instead. Please check for parameter mismatches.
Description Platform Designer may show an “add_instance” warning message from the Nios® V Processor Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition Software v21.4 when, Instantiating the Nios® V Processor Intel® FPGA IP. Performing an IP Upgrade on the same IP from software version 21.3 to 21.4. This is due to a mismatch with the IP version number in the Intel Quartus Prime Software. The full warning message reads as: add_instance: Component intel_niosv_m_unit version 21.1.0 is not installed - loaded latest installed version 21.1.1 instead. Please check for parameter mismatches. Resolution To work around this problem, download and install the patch for the Intel® Quartus® Prime Pro Edition Software v21.4. Download and install Patch for version 21.4 from the following links: Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 for Windows (.exe) Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 for Linux (.run) Readme for Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 (.txt)Why does the QSF assignment get re-ordered after the IP upgrade in the Quartus® Prime Pro Edition Software version 24.1?
Description As FPGA Intellectual Property (IP) solutions have replaced Nios® V Processor for FPGA for Nios II Processor for FGPA from the Quartus® Prime Pro Edition Software version 24.1, you may encounter that the QSF assignments in your project could be re-ordered after an IP upgrade to the Quartus® Prime Pro Edition Software version 24.1 resulting in a timing violation after the upgrade. List of IPs affected: H-tile Hard IP Ethernet Intel FPGA IP (Example Design) E-tile Hard IP Ethernet Intel FPGA IP (Example Design) E-tile Hard IP Agilex™ 7 Design Example F-tile Dynamic Reconfiguration Suite FPGA IP Low Latency 100G Ethernet Stratix® 10 FPGA IP 25G Ethernet Stratix® 10 FPGA IP Low Latency E-tile 40G Ethernet FPGA IP Low Latency 50G Ethernet FPGA IP Design Example (Stratix® 10 Device) Stratix® 10 10GBASE-KR PHY IP E-tile Dynamic Reconfiguration FPGA IP Design Example Stratix® 10 10GBASE-KR PHY IP Ethernet Subsystem FPGA IP Arria® 10 Transceiver Native PHY SDI II FPGA IP (Applicable only to Design Example) HDMI FPGA IP (Applicable only to Design Example) DisplayPort FPGA IP (Applicable only to Design Example) F-tile included in the design Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.14 from the appropriate link below. Download patch 0.14 for Windows (quartus-24.1-0.14-windows.exe) Download patch 0.14 for Linux (quartus-24.1-0.14-linux.run) Download the Readme for patch 0.14 (quartus-24.1-0.14-readme.txt) This problem is fixed beginning with the Quartus Prime Pro Edition software version 24.2.Why does the Nios® V processor force Configuration Scheme with Memory Initialization for MAX® 10 FPGA?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and 24.1, you may see an error below when using Dual Compressed Image as the Internal Configuration mode for Nios® V Processor Design on MAX® 10 FPGA, Error (16031): The current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. Note: Assuming that memory initialization is disabled in every on-chip memory. Resolution To work around this problem, Download and install the patches below for the Quartus® Prime Standard Edition Software version 24.1. Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Windows (.exe) Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std (.txt) Download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1. Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Windows (.exe) Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std (.txt) This problem will be resolved in the Quartus® Prime Standard Edition Software version 25.1.Why does my Nios® II/e processor design not generate programming files in the Intel® Quartus® Prime Pro Edition Software v19.1?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v19.1, you may see that designs containing the Nios® II/e processor fail to generate an SRAM Object File (.sof). The following warning may be seen during compilation: Warning(115005): Unlicensed IP: "Nios II Embedded Processor Encrypted output(6AF7 00A2) Resolution To work around this problem, download and install the following patch for the Intel® Quartus® Prime Pro Edition Software v19.1: Version 19.1 patch 0.02 for Windows (.exe) Version 19.1 patch 0.02 for Linux (.run) Readme for the Intel® Quartus® Prime Pro Edition Software v19.1 patch 0.02 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v19.2.Missing C pre-processor macro of “unquoted string” when using Nios® V processor
Description Due to a problem in the Nios®V Processor BSP generation flow in Intel® Quartus® Prime Pro Edition Software version 21.3 to 22.3, the pre-processor macro of data type "unquoted string" cannot be found in the toolchain.cmake file. Specifically, only the “unquoted string” macro assigned with the value “none” may be missing in the toolchain.cmske file. Other string values are not affected. Resolution Please download and install patch 0.04 for Quartus® Prime Pro Edition Software version 22.3 to solve the problem: Patch for Windows OS: Quartus-22.3-0.04-windows.exe Patch for Linux OS: Quartus-22.3-0.04-linux.runWhy does the Nios® V/g processor return inaccurate floating-point calculation results when the Floating-Point Unit is enabled?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1, the Nios® V/g processor might return inaccurate floating-point calculation results when the Floating-Point Unit (FPU) is enabled. This problem is found in Max® 10 FPGA devices only. Other Altera® FPGA devices are not affected. This is because there is a problem in the FPU module, which generates spurious signals affecting the calculation results. Resolution A patch is available to fix this problem for the Quartus® Prime Standard Edition Software version 24.1. Download and install patch 0.03 from the following links: Quartus® Prime Standard Edition Software v24.1 Patch 0.03 This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does the niosv-download utility unable to download the Nios® V processor application ELF file when there are multiple cable instances?
Description The following error message is displayed in the Intel® Quartus® Prime Pro Edition Software version 21.3 and 21.4 when you perform the following tasks: Downloading a Nios® V processor application ELF file into Intel® FPGAs using the niosv-download utility. Generating an OpenOCD configuration file using openocd-cfg-gen utility. INFO: Generating OpenOCD config file. Running "openocd-cfg-gen -c 2 /tmp/niosvm.cfg". Please specify a valid cable ERROR: Failed to generate OpenOCD config file. This error message occurs due to a bug in the openocd-cfg-gen utility, whereby the utility cannot generate the OpenOCD configuration file unless the targeted Intel FPGA is connected to the 1st cable instance. A similar error can be seen when you are using the niosv-download utility because the niosv-download utility also calls out or uses the openocd-cfg-gen utility. You may run the jtagconfig command to display all the connected instances to the host computer. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and 21.4, follow these steps: Ensure that the targeted Intel FPGA is connected to the 1st cable instance. Disconnect other Intel FPGAs from your host computer through the following methods: Power down the devices Unplug the devices from the host computer Download and install the following patch to fix this error in the Intel® Quartus® Prime Pro Edition Software version 21.3: Intel Quartus Prime Pro Software v21.3 Solution Patch 0.33 for Windows (.exe) Intel Quartus Prime Pro Software v21.3 Solution Patch 0.33 for Linux (.run) Readme for Intel Quartus Prime Pro Software v21.3 Solution Patch 0.33 (.txt) Download and install the following patch to fix this error in the Intel® Quartus® Prime Pro Edition Software version 21.4: Intel Quartus Prime Pro Software v21.4 Solution Patch 0.17 for Windows (.exe) Intel Quartus Prime Pro Software v21.4 Solution Patch 0.17 for Linux (.run) Readme for Intel Quartus Prime Pro Software v21.4 Solution Patch 0.17 (.txt) This problem is fixed starting from Intel® Quartus® Prime Pro Edition Software version 22.1.
Why can't I connect two LVDS SERDES instances to one external PLL in Agilex™ 5 device?
Description When trying to implement the structure as shown in “Figure 40. I/O PLL Driving Mixed Receiver and Transmitter Channels in the Same Sub-Bank” of LVDS SERDES User Guide Agilex™ 5 FPGAs and SoCs with two separate LVDS SERDES IP instances and one external IOPLL IP instance, you will see the following fitter error similar to the followings: Error(14996): The Fitter failed to find a legal placement for all periphery components Error(14986): After placing as many components as possible, the following errors remain: Error(175001): The Fitter cannot place 1 CLKGEN, which is within LVDS SERDES IP lvds_serdes_tx_extpll_intel_lvds_2400_mqdyxqy. Error(16234): No legal location could be found out of 7 considered location(s). Reasons why each location could not be used are summarized below: Error(23276): Could not find usable path between source IOPLL: O_LOCK[0] and the CLKGEN: I_PLL_LOCK[0] Resolution For Agilex™ 5, the following rules restrict the LVDS SERDES IP instances placement described above: Each LVDS SERDES IP instance in the mode of TX, RX Non-DPA or RX DPA-FIFO uses one CLKGEN atom. One PLL can only fanout to one CLKGEN atom. Therefore, you cannot connect a single IOPLL to two LVDS IP instances if both of them are in the mode of TX, RX Non-DPA or RX DPA-FIFO. If TX and RX (DPA FIFO or Non-DPA) are sharing the same IOPLL, TX and RX must be generated from a single LVDS IP instance.Why does CMake Error: The source directory "<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN" does not contain CMakeLists.txt. when compiling the Nios® V processor application in Command Line Interface?
Description This problem is observed in Quartus® Prime Pro Edition Software version 21.3 when the command “cmake -G “Unix Makefile” -B software/app/build” is executed to compile the Nios® V processor application for the design example. This is due to missing “-S <path-to-source>“ argument. Without the argument, the cmake command defaults to the current working directory (<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN) as the source directory. For reader’s information about this design example, the design example is provided with a readme.txt. The readme.txt guides user to create CMakeLists.txt for the design example. The BSP CMakeLists.txt is generated by niosv-bsp command, found in <project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN/software/bsp. The APP CMakeLists.txt is generated by niosv-app command, found in <project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN/software/app. There is no CMakeLists.txt in <project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN. However, the snippet of the cmake command in the readme.txt is missing “-S <path-to-source>“ argument. Thus, this error is produced. Resolution To fix this problem, follow one of the following steps: Execute this command: cmake -G "Unix Makefiles" -S software/app/ -B software/app/build The “-S software/app/“ argument adds the CMakeLists.txt path to the source location. OR Change the directory to software/app folder: “cd software/app”. Then, execute the command: make -G "Unix Makefiles" -B build This problem is fixed starting with the Quartus® Prime Pro Edition Software version 21.4. The readme.txt is corrected with “cmake -G "Unix Makefiles" -S software/app/ -B software/app/build“Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829