Why am I seeing the Error: pgm_q_inst_intel_niosv_g_0_platform_irq_rx_bfm_ip.pgm_q_inst_intel_niosv_g_0_platform_irq_rx_bfm: "Irq width" (AV_IRQ_W) 2048 is out of range: 1-32?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and Quartus® Prime Standard Edition Software 24.1, the error message might occur when generating a testbench system for Nios® V/g processor designs. As a result, the Quartus® Prime software fails to generate the testbench system. The error message occurs when ALL the following conditions are met: The processor implements CLIC interrupt mode with more than 32 platform interrupts (Number of Platform interrupt sources parameter). The processor’s interrupt receiver is exported to the top-level system (Double-click to export option). Selected Standard, BFMs for standard Platform Designer interfaces when generating testbench system (Generate Testbench System tools). This is because the maximum width of the Avalon Interrupt Source and Interrupt Sink BFMs is capped at 32 interrupts. Resolution To work around this problem in the Quartus® Prime software, you may proceed with any of the following options: Implements CLIC interrupt mode with fewer than 32 platform interrupts. Refrain from exporting the processor’s interrupt receiver. Selects Simple, BFM for clocks, and resets when generating the testbench system. Additional Information This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software and Quartus® Prime Standard Edition Software. Related Articles Nios® V General Purpose Processor (Number of Platform interrupt sources Parameter) Quartus® Prime User Guide (Generating the Testbench System Tool) Avalon® Interrupt Source and Interrupt Sink BFMs (IRQ Width Parameter)How do I install Cygwin for SoCEDS?
Description Starting with Quartus® Prime Standard and Pro Edition Software version 19.1 for Windows® and the Altera® SoC FPGA Embedded Development Suite (SoC EDS) version 19.1 for Windows, the Cygwin component must be installed manually. Administrative privileges are needed on the PC to perform the Cygwin installation. Resolution The procedure for installing Cygwin is as follows: Go to the official Cygwin website https://cygwin.com/ Download the 64bit installer (setup-x86_64.exe) Open a Windows Command Prompt Locate the path where Cygwin will be installed. For SoC EDS, the default path is C:\intelFPGA_pro\<version>1\embedded\host_tools\cygwin Run the installer in the Command Prompt with the following parameters (replace <<Path Cygwin Installer>> with the correct path): setup-x86_64.exe --wait --quiet-mode --root <<<Path Cygwin installer>> --site http://cygwin.mirrors.hoobly.com --packages make,gcc-core,gcc-g ,ncurses,inetutils,openssh,mosh,patch,flex,bison,tar,bzip2,zip,unzip,util-linux,git,subversion,vim,xxd,m4,wget,dos2unix,libintl devel,diffutils,libncurses-devel,iperf,xorg-server,xinit,mingw64-x86_64-gcc-core,mingw64-x86_64-gcc-g Make sure the command is all on a single line. Copying and pasting from this document may split the command into multiple lines. Press Enter to issue the command and wait until everything is automatically installed.Why does the Nios® V processor fail to generate HDL and report "Error: add_fileset_file" in the Quartus® Prime Standard Edition Software?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This problem is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl calls add_fileset_file on a simulator, which is not supported in Windows OS. The simulators are Cadence Simulator, Synopsys VCS*, and VCS MX. For information on the simulators' supported platforms, refer to Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators. Resolution To work around this problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, follow these steps: Navigate to the following hw.tcl files: <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_dbg_mod_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_common/intel_niosv_timer_msip_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_g/intel_niosv_g_unit_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_m/intel_niosv_m_unit_hw.tcl <Quartus Std installation folder>/ip/altera/soft_processor/intel_niosv_c/intel_niosv_c_unit_hw.tcl Inside each hw.tcl file, find set simulators [list ]. Modify the subsequent if-else statement to, set simulators [list ] if {$sim_synth == "sim" } { if { [file exists intelfpga] && [file isdirectory intelfpga] } { set simulators [list intelfpga] } elseif { $::tcl_platform(platform) == "windows" } { set simulators [list aldec mentor] } else { set simulators [list aldec cadence mentor synopsys] } } The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1 and Quartus® Prime Standard Edition software version 25.1.Why does the Nios® V processor fail to generate HDL with an add_fileset_file error message in Quartus® Prime Standard Edition from Windows* OS?
Description Due to a problem in the Quartus® Prime Standard Edition Software versions 22.1, 23.1, and 24.1, the Nios® V processor might fail to generate HDL with an error message about add_fileset_file. This issue is present only on Windows OS. Example error message: Error: add_fileset_file: No such file <Nios V processor SystemVerilog file> while executing “add_fileset_file $current_sim/<Nios V processor SystemVerilog file> SYSTEM_VERILOG PATH $current_sim/<Nios V processor SystemVerilog file> $attr” This is because the Nios® V processor hw.tcl is calling add_fileset_file on an unsupported simulator. These unsupported simulators are referring to simulators that are not supported in Windows* OS - Cadence Simulator and Synopsys VCS* and VCS MX. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patches below. The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.1.1 and Quartus® Prime Standard Edition software version 25.1. Additional Information For information on the simulators’ supported platforms, refer to the Quartus® Prime Standard Edition User Guide: Third-party Simulation - Supported Simulators.Why does the Nios® V processor force Configuration Scheme with Memory Initialization for MAX® 10 FPGA?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and 24.1, you may see an error below when using Dual Compressed Image as the Internal Configuration mode for Nios® V Processor Design on MAX® 10 FPGA, Error (16031): The current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. Note: Assuming that memory initialization is disabled in every on-chip memory. Resolution To work around this problem, Download and install the patches below for the Quartus® Prime Standard Edition Software version 24.1. Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Windows (.exe) Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std (.txt) Download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1. Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Windows (.exe) Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std (.txt) The problem has been fixed starting with Quartus® Prime Standard Edition software version 25.1,Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software versions 24.3.1, 25.1, and 25.1.1, and Quartus® Prime Standard Edition Software version 24.1. When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) The problem has been fixed starting with Quartus® Prime Pro Edition software version 25.3 and Quartus® Prime Standard Edition software version 25.1.Why does the Nios® V/g processor return inaccurate floating-point calculation results when the Floating-Point Unit is enabled?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1, the Nios® V/g processor might return inaccurate floating-point calculation results when the Floating-Point Unit (FPU) is enabled. This problem is found in MAX® 10 FPGA devices only. Other Altera® FPGA devices are not affected. This is because there is a problem in the FPU module, which generates spurious signals affecting the calculation results. Resolution A patch is available to fix this problem for the Quartus® Prime Standard Edition Software version 24.1. Download and install patch 0.03 from the following links: Quartus® Prime Standard Edition Software v24.1 Patch 0.03 The problem has been fixed starting with Quartus® Prime Standard Edition software version 25.3.add_instance: Component intel_niosv_m_unit version <x.y> is not installed - loaded latest installed version <x.y> instead. Please check for parameter mismatches.
Description Platform Designer may show an “add_instance” warning message from the Nios® V Processor Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition Software v21.4 when, Instantiating the Nios® V Processor Intel® FPGA IP. Performing an IP Upgrade on the same IP from software version 21.3 to 21.4. This is due to a mismatch with the IP version number in the Intel Quartus Prime Software. The full warning message reads as: add_instance: Component intel_niosv_m_unit version 21.1.0 is not installed - loaded latest installed version 21.1.1 instead. Please check for parameter mismatches. Resolution To work around this problem, download and install the patch for the Intel® Quartus® Prime Pro Edition Software v21.4. Download and install Patch for version 21.4 from the following links: Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 for Windows (.exe) Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 for Linux (.run) Readme for Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 (.txt)Why does the QSF assignment get re-ordered after the IP upgrade in the Quartus® Prime Pro Edition Software version 24.1?
Description As FPGA Intellectual Property (IP) solutions have replaced Nios® V Processor for FPGA for Nios II Processor for FGPA from the Quartus® Prime Pro Edition Software version 24.1, you may encounter that the QSF assignments in your project could be re-ordered after an IP upgrade to the Quartus® Prime Pro Edition Software version 24.1 resulting in a timing violation after the upgrade. List of IPs affected: H-tile Hard IP Ethernet Intel FPGA IP (Example Design) E-tile Hard IP Ethernet Intel FPGA IP (Example Design) E-tile Hard IP Agilex™ 7 Design Example F-tile Dynamic Reconfiguration Suite FPGA IP Low Latency 100G Ethernet Stratix® 10 FPGA IP 25G Ethernet Stratix® 10 FPGA IP Low Latency E-tile 40G Ethernet FPGA IP Low Latency 50G Ethernet FPGA IP Design Example (Stratix® 10 Device) Stratix® 10 10GBASE-KR PHY IP E-tile Dynamic Reconfiguration FPGA IP Design Example Stratix® 10 10GBASE-KR PHY IP Ethernet Subsystem FPGA IP Arria® 10 Transceiver Native PHY SDI II FPGA IP (Applicable only to Design Example) HDMI FPGA IP (Applicable only to Design Example) DisplayPort FPGA IP (Applicable only to Design Example) F-tile included in the design Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.14 from the appropriate link below. Download patch 0.14 for Windows (quartus-24.1-0.14-windows.exe) Download patch 0.14 for Linux (quartus-24.1-0.14-linux.run) Download the Readme for patch 0.14 (quartus-24.1-0.14-readme.txt) This problem is fixed beginning with the Quartus Prime Pro Edition software version 24.2.Why does my Nios® II/e processor design not generate programming files in the Intel® Quartus® Prime Pro Edition Software v19.1?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software v19.1, you may see that designs containing the Nios® II/e processor fail to generate an SRAM Object File (.sof). The following warning may be seen during compilation: Warning(115005): Unlicensed IP: "Nios II Embedded Processor Encrypted output(6AF7 00A2) Resolution To work around this problem, download and install the following patch for the Intel® Quartus® Prime Pro Edition Software v19.1: Version 19.1 patch 0.02 for Windows (.exe) Version 19.1 patch 0.02 for Linux (.run) Readme for the Intel® Quartus® Prime Pro Edition Software v19.1 patch 0.02 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v19.2.
