How to install the Windows* Subsystem for Linux* (WSL) on Windows* OS?
Description Starting with the Nios® II EDS in the Intel® Quartus® Prime Pro Edition Software version 19.2 and Intel® Quartus® Prime Standard Edition Software version 19.1, the Cygwin component in the Windows* version of Nios II EDS has been removed and replaced with WSL. Resolution The procedure for installing WSL is: Follow standard instructions from Microsoft® to install Ubuntu* 18.04 LTS for WSL. Refer to https://docs.microsoft.com/en-us/windows/wsl/install-win10. The recommended OS would be Windows* 10 build version 16215.0 or higher. NIOS II currently does not support WSL 2. Remember: In Windows Features, ensure to turn on the Windows Subsystem for Linux option. After the installation is successful, launch the Ubuntu 18.04 app. Install the additional distro packages that are required for Nios® II EDS using the following commands: a. sudo apt update b. sudo apt install wsl c. sudo apt install dos2unix d. sudo apt install make e. sudo apt install build-essential Note: Ensure that all package dependencies, repositories lists, and Internet connections for WSL are set correctly. For Nios II Command Shell, launch the Windows executables of the command line tools by adding ".exe" (for example eclipse-nios2.exe or jtagconfig.exe). Nios II BSP and application projects from the previous Intel Quartus Prime release are not compatible with the WSL solution. You are required to regenerate your projects. This information now included in the Nios II Software Developer Handbooknios2-elf-gcc.exe: error: CreateProcess: No such file or directory
Description Due to a recent Windows update from Microsoft®, the Nios® II build flow using Windows Subsystem for Linux (WSL) is presenting issues during project compilation and download. The failure has been identified in computers running Windows 10 Version 1903 and later. The failure is not presented in Windows 10 Version 1809 or earlier. Some of the error messages include: nios2-elf-gcc.exe: error: CreateProcess: No such file or directory nios2-elf-g .exe: error: missing argument to '-msys-lib=' wslpath: /...........elf.srec: No such file or directory Resolution Patches to fix this problem are available for the Intel® Quartus® Prime Pro and Standard Editions. For Pro versions: Download patch for Intel® Quartus® Prime Pro Edition Software version 20.3 Download patch for Intel® Quartus® Prime Pro Edition Software version 20.2 Download patch for Intel® Quartus® Prime Pro Edition Software version 20.1 Download patch for Intel® Quartus® Prime Pro Edition Software version 19.4 Download patch for Intel® Quartus® Prime Pro Edition Software version 19.3 Download patch for Intel® Quartus® Prime Pro Edition Software version 19.2 For Standard versions: Download patch for Intel® Quartus® Prime Standard Edition Software version 20.1 Download patch for Intel® Quartus® Prime Standard Edition Software version 19.1 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4 and the Intel® Quartus® Prime Standard Edition Software version 20.1.1.What is the Adjusted Peak Performance (APP) for the Nios II Processor?
Description APP is an adjusted peak rate at which "digital computers" perform 64-bit or larger floating point additions and multiplications. APP is expressed in Weighted TeraFLOPS (WT), in units of 10**12 adjusted floating point operations per second. Below is an outline of how the "APP" is calculated : n number of processors in the "digital computer" i processor number (i,....n) ti processor cycle time (ti = 1/Fi) Fi processor frequency Ri peak floating point calculating rate Wi architecture adjustment factor 1. For each processor i, determine the peak number of 64-bit or larger floating-point operations, FPOi, performed per cycle for each processor in the "digital computer". Note: In determining FPO, include only 64-bit or larger floating point additions and/or multiplications. All floating point operations must be expressed in operations per processor cycle; operations requiring multiple cycles may be expressed in fractional results per cycle. For processors not capable of performing calculations on floating-point operands of 64-bits or more the effective calculating rate R is zero. 2. Calculate the floating point rate R for each processor Ri = FPOi/ti. 3. Calculate APP as APP = W1 x R1 W2 x R2 … Wn x Rn. 4. For "vector processors", Wi = 0.9. For non-"vector processors", Wi = 0.3. The first determination an exporter must make is whether the computer is capable of performing 64-bit or larger floating-point arithmetic. If it is not, the WT value is zero. The APP (Adjusted Peak Performance) for a single Nios II processor equals 0, since the Nios II does not have native 64-bit floating point support. However, keep in mind that the APP should be considered somewhat of a systems metric, and its value is dependent on how the overall system is designed. For example, if you create a custom instruction to add 64-bit floating point support to a single Nios II, or if you were to use multiple Nios II's on your chip to build 64-bit floating point support, or if you add multiple FPGAs to your board each with a different memory for the processors in it to create 64-bit floating point support, then, you would probably end up with a different non-zero APP value for each case. Therefore, due to the many possible variables that need to be considered in the APP calculation that are outside of Altera's direct knowledge or control, the actual APP value for an end system can only be correctly calculated and determined by the designer or user of the particular system. But for most designs solely composed of Nios II processors, the APP should usually be well below the 0.75 WT (Weighted Tera-Flops) value that the United States Department of Commerce is worried about. For more information, refer to the "Practitioner's Guide To Adjusted Peak Performance" document, which is provided by the United States Department of Commerce Bureau of Industry and Security: http://www.bis.doc.gov/hpcs/app-wtpractitionersguidefeb22with-cover.pdfWhy does niosv-stack-report return error during Nios® V build flow in RiscFree* IDE for Intel® FPGAs?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, this problem may be seen in RiscFree* IDE for Intel® FPGAs when building the Nios® V processor software. The error descriptions are shown as followed make: *** [Makefile:91: all] Error 2 make[1]: *** [CMakeFiles/Makefile2:156: CMakeFiles/niosv-stack-report.dir/all] Error 2 make[1]: *** Waiting for unfinished jobs.... make[2]: *** [CMakeFiles/niosv-stack-report.dir/build.make:73: app.elf.stack_report] Error 127 The niosv-stack-report utility is only present in Intel® Quartus® Prime Pro Edition Software. The error message above would occur when building the application if, RiscFree* IDE for Intel® FPGAs is installed as a standalone development tool with the Intel® Quartus® Prime Programmer RiscFree* IDE for Intel® FPGAs is not launched from the Nios® V Command Shell Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, do these in any order: You may ignore this error and proceed as usual. The necessary software build files (such as .elf file and .objcopy file) will be created and are not affected by this error Launch the RiscFree* IDE for Intel® FPGAs from the Nios® V Command Shell This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3.Nios® II Boot from EPCQ or EPCS in Quartus® II 13.1
Description Due to a problem in the Quartus II software, the Quartus Programmer must be used to program EPCQ devices using a generated .jic file in order to enable 4 bytes addressing mode. The nios2-flash-programmer is then required to program the EPCS/EPCQ device with the .flash file generated by the sof2flash tool in order to include the header information required by the new Nios II bootcopier. The new Nios II bootcopier introduced in Quartus® II 13.1 requires a new work flow. Resolution To enable the Nios II processor to load software from EPCS / EPCQ after power cycle or reset in the Quartus II software version 13.1 and later follow the steps below: 1. Add the following 2 lines in your <project>.qsf file. a. set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1" b. set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON 2. Delete the “db”, “incremental_db” and “qsys generated folders” in your project directory. 3. Make sure the Nios II’s Reset Vector is pointing at EPCS/EPCQ Controller. 4. Make sure the Nios II’s Exception Vector is pointing at onchip_memory or some other memory devices. 5. Generate in Qsys. 6. Compile in Quartus II. 7. Note: If the design is not targeting EPCQ device, skip this step Generate the .jic file with “Convert Programming File” tool. a. Select .jic file for “Programming file type”. b. Select the correct EPCQ device for “Configuration device”. c. Make sure “Active Serial” is selected for “Configuring device mode”. d. Click on “Flash Loader”, then click on “Add Device” to select the device you’re using then clicks “Ok”. e. Click on “SOF Data”, and then click on “Add File” to select the .sof file generated by Quartus II compilation. f. Click on the .sof file you have just added, click on “Properties” and enable the “Compression” from there. g. Click on “Generate” to generate the .jic file. h. Program the EPCQ with the .jic file generated with Quartus Programmer and power-cycle the board. 8. Generate the .flash files for the .sof and .elf files with: a. sof2flash --input=hw.sof --output=hw.flash --XX –verbose Note: Replace XX with EPCS for EPCS device and replace XX with EPCQ for EPCQ device b. elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose 9. Use nios2-configure-sof or Quartus Programmer to configure the FPGA with the .sof file then program the EPCQ device with the Nios II Flash Programmer as follow: a. nios2-flash-programmer --epcs --base=<base address of EPCQ device> hw.flash Note: The EPCQ need to be programmed with the .flash file even if it had been programmed with Quartus Programmer earlier in .jic format b. nios2-flash-programmer --epcs --base=<base address of EPCQ device> sw.flashError: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.How do I program an EPCS device with a SOF file and Nios® II ELF file using the Quartus® II Programmer?
Description The steps needed to generate an EPCS programming file are as follows: Open the Nios II Command Shell (Nios II SDK Shell for pre-6.0 versions) Create a flash file from a SOF using the following command: sof2flash --epcs --input=<sof file name>.sof --output=<flash output file name>.flash --verbose Create a flash file from the ELF using the following command: elf2flash --epcs --base=0x0 --end=<end address> --after=<sof2flash output file name>.flash --input=<elf file name>.elf --output=<flash output file name>.flash Convert the ELF flash file from SREC to HEX nios2-elf-objcopy –input-target srec –output-target ihex <elf2flash output file name>.flash <Hex output file name>.hex The last step will generate a valid HEX file with the correct addressing for an EPCS device. You are now able to use the Quartus II SOF file and the newly created HEX file to create an EPCS programming file. To do this, in Quartus II go to the File menu and choose Convert Programming Files. NOTE: From within the Convert Programming Files window, if you receive an error indicating that the EPCS device does not have enough space for the file then select compression for the SOF file.How do I install Cygwin for SoCEDS?
Description Starting with Intel® Quartus® Prime Standard and Pro Edition Software version 19.1 for Windows® and the Intel® SoC FPGA Embedded Development Suite (SoC EDS) version 19.1 for Windows, the Cygwin component must be installed manually. Administrative privileges are needed on the PC to perform the Cygwin installation. Resolution The procedure for installing Cygwin is as follows: Go to the official Cygwin website https://cygwin.com/ Download the 64bit installer (setup-x86_64.exe) Open a Windows Command Prompt Locate the path where Cygwin will be installed. For SoC EDS, the default path is C:\intelFPGA_pro\<version>1\embedded\host_tools\cygwin Run the installer in the Command Prompt with the following parameters (replace <<Path Cygwin Installer>> with the correct path): setup-x86_64.exe --wait --quiet-mode --root <<<Path Cygwin installer>> --site http://cygwin.mirrors.hoobly.com --packages make,gcc-core,gcc-g ,ncurses,inetutils,openssh,mosh,patch,flex,bison,tar,bzip2,zip,unzip,util-linux,git,subversion,vim,xxd,m4,wget,dos2unix,libintl devel,diffutils,libncurses-devel,iperf,xorg-server,xinit,mingw64-x86_64-gcc-core,mingw64-x86_64-gcc-g Make sure the command is all on a single line. Copying and pasting from this document may split the command into multiple lines. Press Enter to issue the command and wait until everything is automatically installed.Why does CMake Error: The source directory "<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN" does not contain CMakeLists.txt. when compiling the Nios® V processor application in Command Line Interface?
Description This problem is observed in Quartus® Prime Pro Edition Software version 21.3 when the command “cmake -G “Unix Makefile” -B software/app/build” is executed to compile the Nios® V processor application for the design example. This is due to missing “-S <path-to-source>“ argument. Without the argument, the cmake command defaults to the current working directory (<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN) as the source directory. For reader’s information about this design example, the design example is provided with a readme.txt. The readme.txt guides user to create CMakeLists.txt for the design example. The BSP CMakeLists.txt is generated by niosv-bsp command, found in <project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN/software/bsp. The APP CMakeLists.txt is generated by niosv-app command, found in <project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN/software/app. There is no CMakeLists.txt in <project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN. However, the snippet of the cmake command in the readme.txt is missing “-S <path-to-source>“ argument. Thus, this error is produced. Resolution To fix this problem, follow one of the following steps: Execute this command: cmake -G "Unix Makefiles" -S software/app/ -B software/app/build The “-S software/app/“ argument adds the CMakeLists.txt path to the source location. OR Change the directory to software/app folder: “cd software/app”. Then, execute the command: make -G "Unix Makefiles" -B build This problem is fixed starting with the Quartus® Prime Pro Edition Software version 21.4. The readme.txt is corrected with “cmake -G "Unix Makefiles" -S software/app/ -B software/app/build“Why does the Qsys on-chip memory (RAM or ROM) content get corrupted after asynchronous reset?
Description The on-chip memory (RAM or ROM) content may get corrupted after asynchronous reset. The asynchronous reset assertion to the logic driving the address bus of the FPGA embedded memory can cause asynchronous logic propagation. This can cause multiple address lines into the embedded memory to become asserted simultaneously, which can cause charge sharing between bit cells, corrupting the contents of the embedded memory. The current Qsys reset implementation does not include specific handling logic to protest against such memory corruption issue. This can cause a functional failure in your design where the memory contents need to be preserved at all time, such as when the on-chip memory is used to store Nios II processor software. If the memory content is corrupted after asynchronous reset, the Nios II processor may stall when executing corrupted instruction code from the memory. The stalled processor is unrecoverable and FPGA reconfiguration is required to fix the problem. Resolution If you encounter similar issue in your system that uses Qsys on-chip memory, you can apply device patch DP2 for Quartus II software version 13.0 to fix the problem. To obtain the patch, visit http://software.altera.com/ This issue will be fixed in future releases of Quartus II software starting with version 13.0 SP1. This issue affects other Altera intellectual properties (IP) including the Altera UniPHY memory controller and transceiver reconfiguration controller. To learn more, refer to solution rd05212013_358 and rd05022013_457. Related Articles Why does the Transceiver Reconfiguration Controller's reconfig_busy output get stuck high after a reset? Why assertion of reset may cause low probablity lock up of UniPHY NIOS sequencer resulting in incomplete calibration
