Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.How can I migrate my Nios II processor design to the Nios II Gen 2 processor?
Description The Nios ® II Gen 2 processor is introduced in the Quartus ® II software version 14.0. A migration script is provided for users to migrate from the Nios II processor to the Nios II Gen 2 processor. Resolution To migrate your existing Qsys design to the Nios II Gen 2 processor, follow these steps: Download “nios2_gen2_migration.tcl" and put the script in your project directory Run Nios II Command Shell in Window system or Console in Linux System Browse to your project directory and run below command: qsys-script --script= nios2_gen2_migration.tcl --system-file=<qsys_file>.qsys Regenerate Qsys and recompile your project after appling the TCL script in Quartus II and run “generate bsp-editor” in Nios II EDS. Related Articles How can I migrate the Nios II processor /s core to an equivalent Nios II Gen 2 processor /f core ?Why does building the Nios® V software project fail in the network server that implements UNC paths?
Description Due to a software problem in Ashling RiscFree IDE for Quartus® Prime Pro Edition Software version 24.1 in dealing with the UNC path, you might see the below errors: ../riscv32-unknown-elf/bin/ld.exe: cannot find -lc: Invalid argument ../riscv32-unknown-elf/bin/ld.exe: cannot find -lstdc++: Invalid argument ../riscv32-unknown-elf/bin/ld.exe: cannot find -lgcc: Invalid argument ../riscv32-unknown-elf/bin/ld.exe: cannot find -lm: Invalid argument collect2.exe: error: ld returned 1 exit status UNC path is used to access network resources and must be in the format specified by the Universal Naming Convention. Resolution Workaround: A patch is available to fix this problem for the Ashling RiscFree IDE for Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.01rf from the attached zip file. Zip file Zip file content: Patch 0.01rf for Ashling RiscFree 24.1 for Windows (.exe) Readme for Patch 0.01rf for Ashling RiscFree 24.1 for Windows (.txt) Related Information: File path formats on Windows systems - .NET | Microsoft Learn For more information on the difference between traditional DOS and UNC paths in Windows systems.Why does Nios® V/g processor fail to debug when Instruction Tightly Coupled Memory (TCM) is enabled in the design?
Description Due to a problem with the Nios® V/g processor in the Quartus® Prime Pro Edition Software version 23.3, the debugger can not access Instruction TCM in a Nios® V/g processor design. Resolution This problem is caused by the exclusive allocation of instruction memory in Instruction TCM, preventing its use as both instruction and data memories. This problem is fixed in Quartus® Prime Pro Edition Software version 23.4 and later versions.Why do my Nios II system instructions get corrupted when Nios II ECC error occurs ?
Description Due to a problem in the Quartus® II software version 13.1, if the Nios II processor is configured with ECC enabled, ECC errors can cause invalid instruction cache operation. The invalid instruction cache operation is the result of the ECC corrupted instruction word. Resolution This problem has been fixed beginning with the Quartus II software version 14.0.Error: "Makefile is not up to date"
Description Due to an issue with the Nios® II Embedded Design Suite (EDS), sometimes the tool is not able to update the makefile of the project and gives the following error message: ****************** make all Makefile not up to date. settings.bsp has been modified since the BSP Makefile was generated. Generate the BSP to update the Makefile, and then build again. To generate from Eclipse: 1. Right-click the BSP project. 2. In the Nios® II Menu, click Generate BSP. To generate from the command line: nios2-bsp-generate-files --settings= --bsp-dir= make: *** [makefile] Error 1 ************************************ After following the given instructions, the error still exists because the compiler finds the Makefile isn't up to date after editing and regenerating the BSP. Resolution To overcome this issue, do the following: Open the BSP project folder. Right-click the Makefile >> Delete. Open the Nios® II Command Shell. Write the following command: cd <...../project_bsp> nios2-bsp-generate-files --settings=settings.bsp --bsp-dir= <...../project_bsp/> Build your project again.Why does the QSF assignment get re-ordered after the IP upgrade in the Quartus® Prime Pro Edition Software version 24.1?
Description As FPGA Intellectual Property (IP) solutions have replaced Nios® V Processor for FPGA for Nios II Processor for FGPA from the Quartus® Prime Pro Edition Software version 24.1, you may encounter that the QSF assignments in your project could be re-ordered after an IP upgrade to the Quartus® Prime Pro Edition Software version 24.1 resulting in a timing violation after the upgrade. List of IPs affected: H-tile Hard IP Ethernet Intel FPGA IP (Example Design) E-tile Hard IP Ethernet Intel FPGA IP (Example Design) E-tile Hard IP Agilex™ 7 Design Example F-tile Dynamic Reconfiguration Suite FPGA IP Low Latency 100G Ethernet Stratix® 10 FPGA IP 25G Ethernet Stratix® 10 FPGA IP Low Latency E-tile 40G Ethernet FPGA IP Low Latency 50G Ethernet FPGA IP Design Example (Stratix® 10 Device) Stratix® 10 10GBASE-KR PHY IP E-tile Dynamic Reconfiguration FPGA IP Design Example Stratix® 10 10GBASE-KR PHY IP Ethernet Subsystem FPGA IP Arria® 10 Transceiver Native PHY SDI II FPGA IP (Applicable only to Design Example) HDMI FPGA IP (Applicable only to Design Example) DisplayPort FPGA IP (Applicable only to Design Example) F-tile included in the design Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.14 from the appropriate link below. Download patch 0.14 for Windows (quartus-24.1-0.14-windows.exe) Download patch 0.14 for Linux (quartus-24.1-0.14-linux.run) Download the Readme for patch 0.14 (quartus-24.1-0.14-readme.txt) This problem is fixed beginning with the Quartus Prime Pro Edition software version 24.2.Is Nios® II EDS supported on Windows 10?
Description In the readme.txt, it was mentioned that Windows 10 does not support Nios® II EDS Standard edition. https://www.intel.com/content/dam/altera-www/global/en_US/others/download/os-support/readme-qp171.txt However, in what's New in Nios® II, it is supported. https://www.altera.com/products/processors/what_s-new.html Resolution Nios® II EDS is supported for Windows 10 as stated in What's New Page: https://www.altera.com/products/processors/what_s-new.html A correction will be applied to the readme.txt file in future Quartus® Prime releases.Why isn't my Nios II detected when using the Nios II Hardware v2(beta) launcher in Eclipse for Nios II?
Description Due to a problem in the Quartus® software version 16.0.1, Eclipse for Nios® II may fail to detect Nios II hardware when using the Nios II Hardware v2(beta) launcher. The configuration window may show: Unable to communicate with system console. Resolution To overcome this issue use the non-beta launcher, or Launch NiosII Eclipse SBT From Nios II menu bar, run System console, and wait for this console to finalize its startup (device detection) Right click on the application folder, Run As > Run Configurations > Nios II Hardware v2 (beta). The Nios II instance should be found and Running/debugging can be launched. This problem is scheduled to be fixed in a future relase of the Quartus software.How can I set the UART HAL driver to operate in non-blocking mode with the Nios II processor?
Description The HAL provides two methods to set the UART HAL driver to operate in non-blocking mode. UNIX-Style If using UNIX-style IO function calls you can use the open() function to set a UART to be non-blocking. To do this, open a file descriptor to your UART in the following manner: fd = open("/dev/<your uart name>",O_NONBLOCK | O_RDWR); This file descriptor sets the UART to operate in read/write and non-blocking mode. You can then use the file descriptor with the read() and write() functions. ANSI C If using ANSI C IO function calls you can set a UART HAL driver to operate in non-blocking mode using fcntl(). To do this you need to reference fcntl.h and unistd.h in your source code. Then you can use fcntl() to set the UART to non-blocking mode. Below is an example that sets the STDIN IO channel to operate in non-blocking mode: fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK); For more information, you can reference the HAL API Reference in the Nios ® II Software Developer's Handbook. This document can be found in the following places: Nios II installation - <Nios II installation directory>/documents/n2sw_nii5v2.pdf Altera ® web site - http://www.altera.com/literature/lit-nio2.jsp
