Error: niosv_g_dcache.sv: part-select direction is opposite from prefix index direction
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 24.3.1, 25.1, and Quartus® Prime Standard Edition Software version 24.1 When the Nios® V/g processor is configured with No Data Cache and enabled with Error Detection and ECC Status Reporting, performing Analysis and Synthesis fails with the error "niosv_g_dcache.sv: part-select direction is opposite from prefix index direction". Note that this issue has no relationship with No Instruction Cache. Figure. Nios® V/g Processor Setting to Replicate the Error Resolution To work around this error, Select 1Kbytes Data Cache. Apply a Peripheral Region that covers the whole Nios® V processor’s data_manager address map Enable Error Detection and ECC Status Reporting. By implementing Peripheral Region, the above settings can emulate an ECC-enabled Nios® V processor system that operates without caches. Figure. Workaround (in this example, the whole Nios® V processor’s data_manager address map is 1GB) This problem is scheduled to be fixed in a future release of the Quartus® Prime Edition Software.How to install the Windows* Subsystem for Linux* (WSL) on Windows* OS?
Description Starting with the Nios® II EDS in the Intel® Quartus® Prime Pro Edition Software version 19.2 and Intel® Quartus® Prime Standard Edition Software version 19.1, the Cygwin component in the Windows* version of Nios II EDS has been removed and replaced with WSL. Resolution The procedure for installing WSL is: Follow standard instructions from Microsoft® to install Ubuntu* 18.04 LTS for WSL. Refer to https://docs.microsoft.com/en-us/windows/wsl/install-win10. The recommended OS would be Windows* 10 build version 16215.0 or higher. NIOS II currently does not support WSL 2. Remember: In Windows Features, ensure to turn on the Windows Subsystem for Linux option. After the installation is successful, launch the Ubuntu 18.04 app. Install the additional distro packages that are required for Nios® II EDS using the following commands: a. sudo apt update b. sudo apt install wsl c. sudo apt install dos2unix d. sudo apt install make e. sudo apt install build-essential Note: Ensure that all package dependencies, repositories lists, and Internet connections for WSL are set correctly. For Nios II Command Shell, launch the Windows executables of the command line tools by adding ".exe" (for example eclipse-nios2.exe or jtagconfig.exe). Nios II BSP and application projects from the previous Intel Quartus Prime release are not compatible with the WSL solution. You are required to regenerate your projects. This information now included in the Nios II Software Developer Handbooknios2-elf-gcc.exe: error: CreateProcess: No such file or directory
Description Due to a recent Windows update from Microsoft®, the Nios® II build flow using Windows Subsystem for Linux (WSL) is presenting issues during project compilation and download. The failure has been identified in computers running Windows 10 Version 1903 and later. The failure is not presented in Windows 10 Version 1809 or earlier. Some of the error messages include: nios2-elf-gcc.exe: error: CreateProcess: No such file or directory nios2-elf-g .exe: error: missing argument to '-msys-lib=' wslpath: /...........elf.srec: No such file or directory Resolution Patches to fix this problem are available for the Intel® Quartus® Prime Pro and Standard Editions. For Pro versions: Download patch for Intel® Quartus® Prime Pro Edition Software version 20.3 Download patch for Intel® Quartus® Prime Pro Edition Software version 20.2 Download patch for Intel® Quartus® Prime Pro Edition Software version 20.1 Download patch for Intel® Quartus® Prime Pro Edition Software version 19.4 Download patch for Intel® Quartus® Prime Pro Edition Software version 19.3 Download patch for Intel® Quartus® Prime Pro Edition Software version 19.2 For Standard versions: Download patch for Intel® Quartus® Prime Standard Edition Software version 20.1 Download patch for Intel® Quartus® Prime Standard Edition Software version 19.1 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4 and the Intel® Quartus® Prime Standard Edition Software version 20.1.1.
Why can’t I place the bytes of two LVDS SERDES IP instances (in TX or Non-DPA RX modes) to the same IO sub-bank on Agilex™ 5 in Quartus® Prime Pro Edition Design Software versions prior to 25.3?
Description Due to a problem in Quartus® Prime Pro Edition Design Software versions prior to 25.3, placing both LVDS SERDES IP instances within the same IO sub-bank may not be successful. If you attempt to put the bytes of both IP instances in the same IO sub-bank, you may encounter the following fitter error: Error(14996): The Fitter failed to find a legal placement for all periphery components. Resolution This problem has been fixed in the Quartus® Prime Pro Edition Design Software Version 25.3. Use the Quartus Prime Pro Edition Design Software Version 25.3 to generate the LVDS SERDES IP and compile the project. If you must use the Quartus Prime Pro Edition Design Software versions prior to 25.3, please contact Support with this KDB link. Related Articles Can I distribute the channels of an Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode between two sub-banks? How many IOPLLs are used when implementing Agilex™ 5 FPGA LVDS SERDES IP in RX DPA-FIFO/Soft-CDR mode and distributing the channels between two sub-banks?Nios® II Boot from EPCQ or EPCS in Quartus® II 13.1
Description Due to a problem in the Quartus II software, the Quartus Programmer must be used to program EPCQ devices using a generated .jic file in order to enable 4 bytes addressing mode. The nios2-flash-programmer is then required to program the EPCS/EPCQ device with the .flash file generated by the sof2flash tool in order to include the header information required by the new Nios II bootcopier. The new Nios II bootcopier introduced in Quartus® II 13.1 requires a new work flow. Resolution To enable the Nios II processor to load software from EPCS / EPCQ after power cycle or reset in the Quartus II software version 13.1 and later follow the steps below: 1. Add the following 2 lines in your <project>.qsf file. a. set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1" b. set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON 2. Delete the “db”, “incremental_db” and “qsys generated folders” in your project directory. 3. Make sure the Nios II’s Reset Vector is pointing at EPCS/EPCQ Controller. 4. Make sure the Nios II’s Exception Vector is pointing at onchip_memory or some other memory devices. 5. Generate in Qsys. 6. Compile in Quartus II. 7. Note: If the design is not targeting EPCQ device, skip this step Generate the .jic file with “Convert Programming File” tool. a. Select .jic file for “Programming file type”. b. Select the correct EPCQ device for “Configuration device”. c. Make sure “Active Serial” is selected for “Configuring device mode”. d. Click on “Flash Loader”, then click on “Add Device” to select the device you’re using then clicks “Ok”. e. Click on “SOF Data”, and then click on “Add File” to select the .sof file generated by Quartus II compilation. f. Click on the .sof file you have just added, click on “Properties” and enable the “Compression” from there. g. Click on “Generate” to generate the .jic file. h. Program the EPCQ with the .jic file generated with Quartus Programmer and power-cycle the board. 8. Generate the .flash files for the .sof and .elf files with: a. sof2flash --input=hw.sof --output=hw.flash --XX –verbose Note: Replace XX with EPCS for EPCS device and replace XX with EPCQ for EPCQ device b. elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose 9. Use nios2-configure-sof or Quartus Programmer to configure the FPGA with the .sof file then program the EPCQ device with the Nios II Flash Programmer as follow: a. nios2-flash-programmer --epcs --base=<base address of EPCQ device> hw.flash Note: The EPCQ need to be programmed with the .flash file even if it had been programmed with Quartus Programmer earlier in .jic format b. nios2-flash-programmer --epcs --base=<base address of EPCQ device> sw.flashWhy does the Nios® V processor force Configuration Scheme with Memory Initialization for MAX® 10 FPGA?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and 24.1, you may see an error below when using Dual Compressed Image as the Internal Configuration mode for Nios® V Processor Design on MAX® 10 FPGA, Error (16031): The current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. Note: Assuming that memory initialization is disabled in every on-chip memory. Resolution To work around this problem, Download and install the patches below for the Quartus® Prime Standard Edition Software version 24.1. Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Windows (.exe) Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v24.1 Patch 0.01std (.txt) Download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1. Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Windows (.exe) Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std for Linux (.run) Readme for Quartus® Prime Stardand Edition Software v23.1 Patch 0.03std (.txt) This problem will be resolved in the Quartus® Prime Standard Edition Software version 25.1.Why does Nios® V processor design example script returns error "riscv-none-embed-objcopy: command not found"?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and RiscFree* IDE for Intel® FPGAs, this error might be seen when running the Nios® V processor design example script. This is because the script is not using the RISC-V GNU Compiler Toolchain provided in the RiscFree* IDE for Intel® FPGAs. Resolution To work around this error in the Intel® Quartus® Prime Pro Edition Software version 22.2 and RiscFree* IDE for Intel® FPGAs, do the following: Change the command "riscv-none-embed-objcopy" to "riscv32-unknown-elf-objcopy" This problem is currently being fixed in the Intel® Quartus® Prime Pro Edition Software version 22.3.Why am I seeing Deterministic Latency Accuracy problems when using Inter-protocol Designs in the GTS Dynamic Reconfiguration Controller IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3 and earlier, you may inter-protocol GTS Ethernet Hard IP with PTP and GTS CPRI IP in GTS Dynamic Reconfiguration Controller IP designs. Resolution Currently, there is no workaround for this problem. This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software. Related IP Core GTS Dynamic Reconfiguration Controller IP GTS Ethernet Hard IP with PTP GTS CPRI IPHow do I run a Nios II software application from flash?
Description In order to run Nios® II software from flash, you must provide at least a small bit of volatile memory (RAM) for the .rwdata section, the stack, and the heap. These sections cannot be located in flash because they need to be writeable at runtime. You can run a Nios II software application from flash by following these steps: Ensure your SOPC Builder system contains at least a small amount of RAM (on or off-chip). The amount of RAM required depends on the application. 2 Kbytes should be sufficient for most small C programs. Create your software project in the Nios II IDE In the System Library Properties, set the following sections to flash .text .rodata In the System Library Properties, set the following sections to RAM .rwdata stack heap Build the project in the Nios II IDE Program the development board with the hardware image (SOF) using the Quartus® II Programmer Program the software project into flash using the Flash Programmer in Nios II IDE (Tools menu) Once that has completed, press the CPU reset button to run the software program stored in flash.Nios II GCC compiler options: -march, -mbmx, -mno-bmx, -mcdx, -mno-cdx
Description From nios2-elf-gcc 4.9.2 onwards the Nios® II GCC compiler supports new options: -march, -mbmx, -mno-bmx, -mcdx, -mno-cdx These options cannot be used with the publicly released versions of the Nios II processor and are set to off by default. These options are currently intended only for internal Altera use. Altera has developed a version of the Nios II processor with a modified instruction set encoding (known as R2) that is currently only intended for internal Altera use. Both the R1 (original) and R2 (new) instruction set encodings are supported by the same Nios II GCC compiler in order to streamline compiler development and maintenance. The Nios II R2 instruction set is largely assembly-language upward compatible with the Nios II R1 instruction set, but supports additional mandatory and optional instructions. Resolution The following GCC Nios II R2 compiler options/switches are currently only intended for internal Altera use: -march=<arch> This specifies the revision of the target Nios II architecture/ Instruction Set Architecture (ISA) R1/R2 to be used by the compiler. GCC uses this name to determine which instruction set it should use when generating assembly code. Permissible names are: ‘r1’, ‘r2’. The default setting is \'r1\'. The -march=r2 switch is also accepted by the Nios II assembler, for engineers who are assembling without using the compiler. The following switches require –march=r2 to be specified: -mbmx Enable generation of the architecture-optional Nios II R2 BMX (bit manipulation extension) instructions. -mno-bmx Disable generation of BMX instructions. This is the default. -mcdx Enable generation of the architecture-optional Nios II R2 CDX (code density extension) instructions. -mno-cdx Disable generation of CDX instructions. This is the default.
