Why can't I connect two LVDS SERDES instances to one external PLL in Agilex™ 5 device?

Description

When trying to implement the structure as shown in “Figure 40. I/O PLL Driving Mixed Receiver and Transmitter Channels in the Same Sub-Bank” of LVDS SERDES User Guide Agilex™ 5 FPGAs and SoCs with two separate LVDS SERDES IP instances and one external IOPLL IP instance, you will see the following fitter error similar to the followings:

Error(14996): The Fitter failed to find a legal placement for all periphery components    Error(14986): After placing as many components as possible, the following errors remain:  Error(175001): The Fitter cannot place 1 CLKGEN, which is within LVDS SERDES IP lvds_serdes_tx_extpll_intel_lvds_2400_mqdyxqy.  
Error(16234): No legal location could be found out of 7 considered location(s). Reasons why each location could not be used are summarized below:  
Error(23276): Could not find usable path between source IOPLL: O_LOCK[0] and the CLKGEN: I_PLL_LOCK[0]

Resolution

For Agilex™ 5, the following rules restrict the LVDS SERDES IP instances placement described above:

1. Each LVDS SERDES IP instance in the mode of TX, RX Non-DPA or RX DPA-FIFO uses one CLKGEN atom.
2. One PLL can only fanout to one CLKGEN atom.

Therefore, you cannot connect a single IOPLL to two LVDS IP instances if both of them are in the mode of TX, RX Non-DPA or RX DPA-FIFO.

If TX and RX (DPA FIFO or Non-DPA) are sharing the same IOPLL, TX and RX must be generated from a single LVDS IP instance.