How does the FPGA AI Suite utilize Agilex 5 DSP Blocks?
Hello Altera Community. I have a module called "dot_bf16" that uses the bf16 floating point format to calculate dot product and I am wondering if it uses the Agilex5 AI optimized DSP blocks to do this. I can't myself see how the DSP blocks are configured because they are all encrypted. 1. Agilex™ 5 Variable Precision DSP Blocks Overview • Variable Precision DSP Blocks User Guide Agilex™ 5 FPGAs and SoCs • Altera Documentation and Resources Center This document states that there are 3 operational modes for tensor mode: 1. Tensor float point mode 2. Tensor fixed point mode 3. Tensor accumulation mode Does the FPGA AI Suite utilize any of these? I also noticed the module uses a FSM and controller.
Is Spatial IP ready for LLM / transformer inference?
I am using FPGA AI Suite 2026.1.1 (with the new spatial compiler). Most of the FPGA AI Suite handbook examples I see are classical CNN / vision flows (ResNet-style) on PCIe, hostless JTAG, and SoC. Is transformer / LLM inference (attention layers, variable sequence lengths, large KV-cache activations, etc.) something we can target today with dla_compiler + Spatial IP, or is Spatial still aimed primarily at CNN-like graphs, or is custom RTL expected? And if yes, are there any LLM examples, guides, recommended flows, or known limitations? Thanks,How can I port RTL module into oneAPI FPGA programming ?
Hi there, I have been using oneAPI for FPGA programming for a while. I am now trying to port my well-defined RTL module into my oneAPI implementation. I do read and understand the specification documents provided in oneAPI websites also the openCL SDK development. However, one of these have pointed a very clear way to interact with RTL module using oneAPI. I am successfully runing a combinational vector-add sample myself, but have no idea how to interact with the sythesized modules from oneAPI with clock driven capability and Avalon-ST interface. Have anyone done such a tryout before ? Best.
