Can I connect VCCIO of I/O bank 1 to 2.5 V for AS configuration with EPCQ or EPCQA device when using Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device?
Description No, when you use EPCQ or EPCQA quad-serial configuration device for AS configuration, you cannot connect VCCIO of I/O bank 1 to 2.5 V in Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device. This is because the minimum VOH of the FPGA is insufficient for driving EPCQ or EPCQA input pins. Resolution Use 3.0 V or 3.3 V for Bank 1 VCCIO in Cyclone III, Cyclone IV, and Intel Cyclone 10 LP devices when AS configuration with EPCQ or EPCQA devices is used.Failed to launch MegaWizard™ Plug-In Manager. PLL Intel® FPGA IP v18.0 could not be found in the specified library paths
Description In the Quartus® Prime software version 18.0, when you want to open the MegaWizard™ for editing, you may see error message "Failed to launch MegaWizard™ Plug-In Manager. PLL Intel® FPGA IP v18.0 could not be found in the specified library paths". Resolution To work around this problem, 1) Locate the .lst file of the missing IP in your Intel® FPGA program directory. For example, for the missing PLL, locate "pll_wizard.lst". In the case of Windows: Windows <installation_directory> \ip\altera\altera_pll In the case of Linux: Linux <installation_directory>/linux64/ip/altera/altera_pll 2) Change the text. "<ALIAS>Altera® PLL v18.0</ALIAS>" to "<ALIAS>PLL Intel® FPGA IP v18.0</ALIAS>Failed to launch MegaWizard™ Plug-In Manager. Triple-Speed Ethernet Intel® FPGA IP v18.0 and could not be found in the specified library paths
Description In the Intel® Quartus® Prime Standard Edition Software versions 18.0 and 18.1, when you open the MegaWizard™ for editing, you may see the error message “Failed to launch MegaWizard™ Plug-In Manager. Triple-Speed Ethernet Intel® FPGA IP V18.0 could not be found in the specified library paths”. Resolution To work around this problem in the Intel® Quartus® Prime Standard Edition Software versions 18.0 and 18.1, follow the steps below. 1. Locate altera_eth_tse_wizard.lst in your Intel® FPGA install directory. For Linux System: /linux64/ip/altera/ethernet/altera_eth_tse/altera_eth_tse_wizard.lst For Windows System: /ip/altera/ethernet/altera_eth_tse/altera_eth_tse_wizard.lst 2. Open altera_eth_tse_wizard.lst, add following sentence in a new line after <ALIAS>Triple-Speed Ethernet v17.0</ALIAS> and save. <ALIAS>Triple-Speed Ethernet Intel FPGA IP v18.0</ALIAS> This problem is fixed beginning with the Intel® Quartus® Prime Standard Edition Software version 19.1.Error (10170): Verilog HDL syntax error at source.sv(7) near text: "XXX"; expecting ")
Description Due to a problem in the Intel® Quartus® Prime Standard edition software version 19.1 you will observe this error when you use instantiated typedef enum in a module with an explicit nettype. Resolution To work around this problem, remove the explicit nettype from the module definition. If the Verilog source is part of a library and cannot change, use VERILOG_MACRO with ifdef statement to contain the Verilog code that is handled by the Intel® Quartus® Prime Standard edition software. The name of the VERILOG_MACRO can be defined in the Intel Quartus Setting File (.qsf) with the following assignment: set_global_assignment -name VERILOG_MACRO "<USER_DEFINED>=1"Why is an unconstrained clock error reported when using the Error Message Register Unloader Intel® FPGA IP?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.1 and later, an unconstrained clock is reported in the check timing report in the Timing Analyzer as shown below when using the Error Message Register Unloader Intel® FPGA IP. This problem occurs on Cyclone® V FPGAs. emr_unloader_component|current_state.STATE_CLOCKHIGH ; Node was determined to feed a clock port but was found without an associated clock assignment. emr_unloader_component|crcblock_atom:emr_atom|generate_crcblock_atom.emr_atom~FF_** ; No clock feeds this register's clock port. Resolution To work around this problem, add the create_generated_clock constraint to your SDC file. For example: create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_ports {<clock name>}] [get_keepers {<path to IP>|EMR_unloader0:inst|EMR_unloader0_emr_unloader2_0:emr_unloader2_0|altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH}]Why is there an unconstrained clock reported when using the Error Message Register Unloader IP?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 and earlier, you might see an unconstrained clock reported in the Unconstrained Paths Report in the Timing Analyzer as shown below when using the Error Message Register Unloader IP. *|altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH You will also see critical warning reported during compilation as shown below. This is due to the constraint in the altera_emr_unloader.sdc file that has failed to address the unconstrained clock reported. Critical Warning (332049): Ignored create_generated_clock at altera_emr_unloader.sdc(14): Argument <targets> is an empty collection Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 22.1, follow these steps: In the altera_emr_unloader.sdc file, comment out line 14. Add the create_generated_clock constraint to the altera_emr_unloader.sdc file. For example: create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_pins {*|alt_fault_injection_component|alt_fi_inst|*oscillator|clkout}] [get_keepers { *|emr_unloader_component|current_state.STATE_CLOCKHIGH}] This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does the Intel® FPGA Download Cables drivers installation fail on Windows* operating system?
Description Due to the expiration of the digital signature certificate of the Intel® FPGA Download Cable I (formerly referred to as USB Blaster I download cable) and the Intel® FPGA Download Cable II (formerly referred to as USB Blaster II download cable) drivers for Windows* operating system, the installation process of the drivers may fail. Follow the next steps to verify if the digital signature certificate of your driver has expired: Go to '<Quartus Installation Path>\qprogrammer\quartus\drivers\usb-blaster-ii' folder Right-click on 'usbblasterii.cat' and select 'Properties, then select the 'Digital Signatures' tab Select the 'IFDLII Production Key1' signature from the 'Signature List' and click 'Details' Click on 'View Certificate' If the driver has expired, you will see the 'This certificate has expired or is not yet valid' message Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Software. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Software version 20.4 and the Intel® Quartus® Prime Standard Edition Software version 21.1. Download and install Patch 0.02i for the Intel® Quartus® Prime Pro Edition Programmer and Tools or Patch 0.02stdp for the Intel® Quartus® Prime Standard Edition Programmer and Tools from the appropriate link below. Download Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i for Windows (.exe) Download the Readme for Intel® Quartus® Prime Pro Edition Software version 20.4 patch 0.02i (.txt) Download Intel® Quartus® Prime Standard Edition Software version 21.1patch 0.02stdp for Windows (.exe) Download the Readme for Intel® Quartus® Prime Standard Edition Software version 21.1 patch 0.02stdp (.txt) After installing patch 0.02i or patch 0.02stdp for Windows, follow the next steps to update the driver on the operating system: Connect your Intel FPGA download cable or Intel FPGA download cable II Open Device Manager window of Windows* OS Choose Windows Settings from Start menu > Type “Device Manager” into the search area > Choose Device Manager Find Altera USB-Blaster II under JTAG cables or Altera USB-Blaster under Universal Serial Bus controllers Find USB-Blaster or USB-Blaster II under Other devices Choose Altera USB-Blaster or Altera USB-Blaster II Right-click and choose Update driver from the context menu Choose Browse my computer for driver software on the Update Drivers window Enter the following path for the driver and enable; include subfolders - <Intel Quartus Prime software install directory>\quartus\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\drivers or - <Intel Quartus Prime Programmer install directory>\qprogrammer\quartus\drivers Click Next This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.1.Why is the IEEE 1588 PTP delay/offset measurement is inconsistent on 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP ?
Description Due to a problem with the Intel® Quartus® Prime Software version 21.2 and earlier, the gmii16b_rx_latency of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP output signal may potentially drift between 0 (min) and 0x3FFFFF (max) when Tx clock (tx_serial_clk), Rx clock (rx_cdr_refclk), link partner Tx data channel reference clock and recommended 80MHz latency_measure_clk of the IP core share a common clock source. As a result, the generated Rx timestamps are not accurate, and the measured delay/offset is much larger than expected in IEEE 1588 applications. However, the gmii16b_tx_latency signal is not impacted by this problem. This problem only impacts 1G and 2.5G IEEE 1588 operations. 5G and 10G IEEE 1588 operations are not affected. Resolution Modify IP core latency_measure_clk clock frequency from 80MHz to either 79.98MHz or 80.02MHz to avoid this problem. This modification can also be applied to the 80MHz sampling clock frequency of TOD Synchronizer Intel® FPGA IP and will not affect PTP timestamping accuracy. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.The PLLJ_PLLSPE_INFO.txt file is no longer generated
Description The PLLJ_PLLSPE_INFO.txt file is no longer generated. Resolution Intel® Quartus® development software v16.0 and onwards no longer generates the PLLJ_PLLSPE_INFO.txt file. If this file is needed, refer to the following INI instruction to generate the file: sta_generate_pll_settings_file=on Related Articles Why is the jitter reported in PLLJ_PLLSPE_INFO.txt different than the clock uncertainty calculated by the derive_clock_uncertainty command? Why is a PLLJ_PLLSPE_INFO_M.txt report being generated for a commercial speed grade device?
