Why does the Stratix® 10 EMIF Toolkit report DQS Enable Calibration failure?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, the Intel Stratix® EMIF Toolkit calibration report may show a DQS Enable Calibration failure even though both the DQ/DQS read and write margins show passing valid window values. This DQS Enable Calibration failure report can be ignored if the DQ/DQS read and write margins show passing valid window values. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 19.3 and earlier, you can also verify that the local_cal_success signal is asserted using the Signal Tap Logic Analyzer tool. This problem is fixed in the Quartus Prime Pro Edition Software version 19.4 and later.Why does the Intel® Quartus® Prime Pro Edition software GUI hang after issuing synthesis errors during compilation?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software versions 19.3 and earlier, the Graphical User Interface (GUI) may hang after issuing synthesis errors during compilation. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition software version 19.3. Download and install Patch 0.20 from the appropriate link below. Download patch 0.20 for Windows (.exe) Download patch 0.20 for Linux (.run) Download the Readme for patch 0.20 (.txt). This problem is fixed beginning with version 19.4 of the Intel® Quartus® Prime Pro Edition softwareWhy does my desktop hang when using the SignalTap II Logic Analyzer?
Description Due to a problem in the Quartus® II software versions 10.0 and later, using the SignalTap™ II Logic Analyzer may cause your desktop to hang or become unresponsive to mouse clicks. Specific actions that can trigger this problem include resizing column widths or zooming in or out on data waveforms. This problem is known to affect 64-bit Windows operating systems, but can potentially impact other platforms. Patches are available to fix this problem in the Quartus II software versions 10.1, 10.1 SP1 and 11.0. Download and install the appropriate patch from the links below. Quartus II software version 11.0: Download the version 11.0 patch 0.01 for Windows (.exe) Download the version 11.0 patch 0.01 for Linux (.tar) Download the Readme for the Quartus II software version 11.0 patch 0.01 (.txt) Quartus II software version 10.1 SP1: Download the version 10.1 SP1 patch 1.54 for Windows (.exe) Download the version 10.1 SP1 patch 1.54 for Linux (.tar) Download the Readme for the Quartus II software version 10.1 SP1 patch 1.54 (.txt) Quartus II software version 10.1: Download the version 10.1 patch 0.73 for Windows (.exe) Download the version 10.1 patch 0.73 for Linux (.tar) Download the Readme for the Quartus II software version 10.1 patch 0.73 (.txt) This problem is scheduled to be fixed in a future version of the Quartus II software.Error: Factory com.altera.sopcfactories.QsysFactory reading file - WITH UNICODE CHARACTER.qsys exception com.altera.utilities.altNode.AltNodeException: (in-memory string): Invalid byte 1 of 1-byte UTF-8 sequence. (XML)
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.4, you may see this error when a design using the Avalon® Memory-Mapped Unaligned Burst Expansion IP is migrated from version 20.3 and earlier in Platform Designer. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 20.4, follow the steps below: 1. Download and install Patch 0.18 from the appropriate link below. Download patch 0.18 for Windows (.exe) Download patch 0.18 for Linux (.run) Download README for patch 0.18 (.txt) 2. Remove and re-add all Avalon Memory-Mapped Unaligned Burst Expansion IP files from the Intel® Quartus® Prime Software project. This problem is sceduled to be fixed in a future Intel® Quartus® Prime Pro Edition software release.Internal Error: Sub-system: ASMCC, File: /quartus/comp/asmcc/asmcc_bitfield.cpp, Line: 989
Description Due to a problem in the Quartus II software version 13.0 SP1 and earlier, you may see this error during the Assembler for designs using the right-side PCIe HIP. Resolution A patch is available to fix this problem for the Quartus II software versions 13.0 and 13.0 SP1. Download and install the appropriate from the links below. Quartus II software version 13.0: Download the version 13.0 patch 0.39 for Windows (.exe) Download the version 13.0 patch 0.39 for Linux (.run) Download the Readme for the Quartus II software version 13.0 patch 0.39 (.txt) Quartus II software version 13.0 SP1: Download the version 13.0 SP1 patch 1.12 for Windows (.exe) Download the version 13.0 SP1 patch 1.12 for Linux (.run) Download the Readme for the Quartus II software version 13.0 SP1 patch 1.12 (.txt) This problem is scheduld to be fixed in a future release of the Quartus II software.Why do I see warnings recommending to use auto adaptation mode for CPRI rates that are below 7Gbps of Agilex® 5 FPGA GTS CPRI PHY IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, when you select the board of Agilex® 5 FPGA E-Series 065B Premium Development Kit(ES1) in GTS CPRI PHY IP Example Design tab, and set Manual Adaptation Mode in below 7Gbps profiles, there are warnings: Recommended RX Adaptation mode in the Development Kit selection is Auto for Profile x. Resolution CPRI rates below 7Gbps should use Manual RX Adaptation Mode. You may ignore the warnings. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.Why does configuration fail on Agilex™ 7 FPGA Rev A Development Kits when using Quartus® Prime Pro Edition Software version 21.2?
Description Due to a problem with the Linear Voltage Regulators (LTM46XX) used on some of the Agilex™ 7 FPGA Rev A Development Kits, you may experience configuration failures when using Quartus® Prime Pro Edition Software v21.2. This failure occurs because the voltage required by Agilex™ 7 devices during configuration is higher than the voltage the LTM46XX Regulators are programmed to supply. You might see the following error messages during configuration: Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00800008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Linear Voltage Regulator using a Linear Technologies USB-to PMBus Controller and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following register values for the LTM46XX device: VOUT_MAX = 1.0V VOUT_OV_FAULT_LIMIT = 30% VOUT_OV_WARN_LIMIT = 30% Changing these values will configure the LTM46XX Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to configure successfully.Fatal Error: Read data comes back but dynamic OCT ctrl is not in read mode
Description You may see the following error when you simulate the UniPHY based DDR3 controller in full calibration mode. # ** Fatal: Read data comes back but dynamic OCT ctrl is not in read mode Resolution Open the following file in your simulation file-set: altdq_dqs2_ddio_3reg_<user_device>.sv Find the following line: (1, "Read data comes back but dynamic OCT ctrl is not in read mode"); Replace the line above with the following line: ("Read data comes back but dynamic OCT ctrl is not in read mode at time %f", ); The simulation should run without any errors once the above change is implemented.Is the hard transceiver 8B/10B encoder/decoder in Stratix, Arria, and Cyclone family transceiver devices Fibre Channel compliant?
Description No, the 8B/10B encoder/decoder does not satisfy all the requirements for the Fibre Channel protocol in Stratix® GX, Stratix II GX, Stratix IV GX/T, Arria® GX, Arria II GX, or Cyclone® IV GX devices. 1) Fibre Channel protocol requirements for 1.062 and 2.125 Gbps states that the transmitter needs to start up with negative running disparity. Further, the standard has disparity rules for Ordered Sets. -The embedded 8B/10B encoder does start up with negative disparity. However, the encoder does not contain the functionality to force negative current running disparity at any time. This is required to be able to meet the disparity rules for Ordered Sets. 2) Fibre Channel protocol requirements for "Detection of Invalid transmission Word" for 1.062 and 2.125 Gbps state that Ordered Sets received with incorrect beginning running disparity be flagged as an error. -The current 8B/10B implementation determines running disparity on a character-by-character basis and not Ordered Sets. Due to these non-compliances, customers may or may not be able to use the embedded 8B/10B encoder/decoder in the transceiver megafunction. This decision would have to be based on how the customer is implementing their Fibre Channel or Fibre Channel-like architecture. Possible workarounds: User would have to implement 8B/10B encoding and decoding blocks in the PLD core to be able to meet the specific requirements in both the transmit and receive directions. User could use 8B10B Encoder/Decoder MegaCore Function from Altera Corporation User could use Multi-Gigabit Fibre Channel Transport Core from MorethanIP References: Fibre Channel, Physical Signaling Interface (FC-PH) REV 2.13 December 4, 1991 Fibre Channel Framing and Signaling (FC-FS) REV 1.90Why do I get the error “Error (176286): Found 2 SPI blocks in design” when using Serial Flash Loader Intel® FPGA IP and ASMI Parallel II Intel FPGA IP?
Description This error may be seen if Serial Flash Loader IP and ASMI Parallel II IP is used together in the same design. Both of Serial Flash Loader IP and ASMI Parallel II IP core require ASMI interface access. Therefore, by having both IPs in the same design would cause conflict during compilation as both IPs cannot access the ASMI block at the same time. Resolution To work around this problem, follow the steps below: Turn ON the “Share ASMI interface in the design” check box in Serial Flash Loader IP parameter. Turn ON the “Disable dedicated Active Serial Interface” check box in ASMI Parallel II IP parameter. Route ASMI signals from the ASMI Parallel II IP and connect to the Serial Flash Loader IP ASMI input/output port. Hence, both IPs should be able to share the single ASMI block within Serial Flash Loader IP.