Why do I see warnings recommending to use auto adaptation mode for CPRI rates that are below 7Gbps of Agilex™ 5 FPGA GTS CPRI PHY IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, when you select the board of Agilex™ 5 FPGA E-Series 065B Premium Development Kit(ES1) in GTS CPRI PHY IP Example Design tab, and set Manual Adaptation Mode in below 7Gbps profiles, there are warnings: Recommended RX Adaptation mode in the Development Kit selection is Auto for Profile x. Resolution CPRI rates below 7Gbps should use Manual RX Adaptation Mode. You may ignore the warnings. This problem is scheduled to be fixed in a future version of the Quartus® Prime Pro Edition Software.Why the JAM files generated after compilation are not Real-Time ISP ready?
Description The Real-Time ISP compatible JAM file generation feature is not currently supported as part of the Quartus® Prime Software compilation flow. Resolution To automatically generate a JAM file compatible with the Real-Time ISP feature as part of the Quartus® Prime Software compilation flow, the Automatic Script Execution feature can be used. Follow the next steps to enable the generation of a Real-Time ISP compatible JAM file after the compilation process: 1. Create a TCL script on your project folder with the following line: qexec "quartus_cpf -c <output folder for project results>/<generated pof file> <jam file> -o background_programming=on" 2. Add the following line to your project QSF file: set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:<tcl script>" To verify that the process was successful, open the generated JAM file and look for the following keyword: DO_REAL_TIME_ISP. If this keyword is part of the generated JAM file, then the JAM file is Real-Time ISP ready.Why does configuration fail on Agilex™ 7 FPGA Rev A Development Kits when using Quartus® Prime Pro Edition Software version 21.2?
Description Due to a problem with the Linear Voltage Regulators (LTM46XX) used on some of the Agilex™ 7 FPGA Rev A Development Kits, you may experience configuration failures when using Quartus® Prime Pro Edition Software v21.2. This failure occurs because the voltage required by Agilex™ 7 devices during configuration is higher than the voltage the LTM46XX Regulators are programmed to supply. You might see the following error messages during configuration: Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00800008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Linear Voltage Regulator using a Linear Technologies USB-to PMBus Controller and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following register values for the LTM46XX device: VOUT_MAX = 1.0V VOUT_OV_FAULT_LIMIT = 30% VOUT_OV_WARN_LIMIT = 30% Changing these values will configure the LTM46XX Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to configure successfully.Is there any known issue with Stratix® 10 FPGA Configuration via Protocol (CvP) operation in Quartus® Prime Pro Edition Software version 18.1?
Description You may encounter the following failure when trying to perform the Configuration via Protocol (CvP) operation in Quartus® Prime Pro Edition Software version 18.1: When you perform any Configuration via Protocol operation, there is a small chance that the operation will halt. This issue impacts all Stratix® 10 FPGA production devices. During the Configuration via Protocol (CvP) process, if the bitstream is corrupted after the first 168kB of data, the CVP_CONFIG_ERROR bit in the CvP Status Register goes high. This will cause the Stratix® 10 FPGA device to hang, and another Configuration cannot recover it via a Protocol (CvP) update. This issue impacts all Stratix® FPGA 10 production devices. Resolution Power cycle the Stratix® FPGA device to perform the next Configuration via Protocol (CvP) operation.Why does TimeQuest report the incorrect frequency for coreclkout when using the ATX PLL with the PCIe IP core for Intel® Stratix® V devices?
Description This problem occurs when implementing a Gen 1 or Gen 2 PCIe® IP core using the ATX PLL in the Arria® V GZ or Stratix® V device family. For ES devices, the reported coreclkout is 1/4 the correct frequency. For production devices, the reported coreclkout is 1/2 the correct frequency. This can be seen in TimeQuest using Report Clocks. Both coreclkout and observablecoreclkdiv will have the same incorrectly reported frequency as stated above. Resolution To work around this issue: 1. Compile the design to determine what frequency TimeQuest is reporting. 2. Add the following SDC to constrain the \'coreclkout\': create_clock -period <half of the TimeQuest-reported period> [get_pins -compatibility_mode {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}] For example, if TimeQuest reports a 16ns clock period for a production device, the SDC is: create_clock -period 8.000 [get_pins -compatibility_mode {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|observablecoreclkdiv}] It is important to use the "-compatibility_mode" option to use wildcards within the SDC for get_pins.VHDL simulation is not supported for NCSim and Xcelium simulators in Intel Agilex® 7 FPGA EMIF IP
Description Due to a problem in the prior version of the Intel® Quartus® Prime Pro Edition Software v21.3, a compilation error occurs when NCSim and Xcelium simulators are used. VHDL simulation is not supported in NCSim and Xcelium simulators when generating EMIF IP for designs targeting Intel Agilex® 7 FPGAs. Resolution This issue has been fixed in the Intel® Quartus® Prime Pro Edition Software v21.3 and later versions.Error (210027): Can't use configuration device EPC16 with selected programming mode
Description Due to a problem in the Quartus® II software version 11.1 SP1, the Assembler might generate this error when you compile a design targeting a Stratix® V GX device even if you have not specified an EPC16 device for programming in your project. Resolution To work around this problem, delete the following assignment from your Quartus II Settings File (.qsf): set_global_assignment -name USE_CONFIGURATION_DEVICE ONWhat are the supported migration options for VCCIO pins, when choosing a migration device in the Quartus® II software?
Description The Quartus® II software may direct you to connect a pin to VCCIO or NC when migrating depending upon how the I/O bank and the I/O pins reference the VCCIO in the selected migration device. If there are no I/O pins that reference the VCCIO pin(s) of the migrating device, the Quartus II software will set the VCCIO pin(s) as NC. If there are I/O pins that reference the VCCIO pin(s) of the migrating device, the Quartus II software will set the VCCIO pin(s) as VCCIO. For example, when migrating from a Cyclone® V device 5CEFA5F23I7 to an 5CEFA4F23I7 and comparing both devices, IOBANK_1A does not exist in the 5CEFA5F23I7. Hence, since there are no I/O pins referencing the VCCIO, the Quartus II software will set VCCIO for IOBANK_1A to NC as the migration result. In another example, when migrating from a Cyclone® IV device EP4CE55F29C8 to an EP4CE40F29C8 and comparing both devices, IOBANK_3 exists for both devices, and in this case the Quartus II software will set VCCIO for IOBANK_1A to VCCIO as the migration result. Resolution This problem is fixed in the Quartus II software v14.1.Why do the buttons not work, or why do I get the run-time error "Object doesn't support this property or method" when using the Intel® Arria® 10, Intel® MAX® 10, or Intel® Cyclone® 10 FPGAs Early Power Estimator (EPE) tool?
Description Due to a Microsoft security update, you may experience one of the following symptoms when using the Intel® Arria® 10, Intel® MAX® 10, or Intel® Cyclone® 10 FPGAs Early Power Estimator (EPE) tool: Buttons do not work A run-time error "Object doesn't support this property or method"appears after opening the EPE Resolution To work around this, do the following: Close all Microsoft Office applications including Excel and Word. Open a Windows Explorer, and enter "%temp%" (without quotes) into the address bar. Press "Ctrl" "F" and enter ".exd" (without quotes) into the search box. If any files with extension ".exd" are found, select and delete ALL found files. Enter "%appdata%" (without quotes) into the address bar. Again, press "Ctrl" "F" and search for ".exd", and delete ALL found files. Reopen the EPE. If the issues remain, follow these steps: Open the EPE, go to "File" -> "Info" -> "Compatibility Mode", and click the "Convert" button. If a pop-up appears, click "OK" to proceed with conversion, and then click "Yes" to reopen the workbook. The previous steps convert the original ".xls" EPE file into a ".xlsm" file. The newly created file should not exhibit the original problem. Microsoft's description for this problem can be found at: https://support.microsoft.com/kb/2726958Why does .jic file programming of EPCQ-A devices fail when multiple Intel® Cyclone® 10 LP devices are in the same JTAG chain?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.1, the programming of EPCQ-A devices is executed incorrectly with JTAG Indirect Configuration (.jic) file. You will see the failure when there are more than three Intel® Cyclone® 10 LP devices in a single JTAG chain, where each is connected to an EPCQ-A device as configuration flash. Resolution This problem was fixed in a recent version of the Intel® Quartus® Prime Software.