cc1plus.exe: out of memory allocating 65536 bytes
Description This error may be seen when compiling large software projects on Windows platforms. cc1plus.exe is a 32bit Windows application and has access to 2GB of memory on Windows. Resolution To work around this problem, Windows can be configured to allow 32bit applications access to a 3GB address space. 1. Enable 3GB address space for 32bit applications on Windows: From Windows command prompt run: bcdedit /set IncreaseUserVa 3072 2. Allow cc1plus.exe to use the larger address space From Windows command prompt run: editbin /LARGEADDRESSAWARE "<path>/cc1plus.exe“ This problem is scheduled to be fixed in a future release of the SoC EDS Software.What do the [GND Clamp] and [POWER Clamp] keywords describe in an input/output buffer information specification (IBIS) model?
Description The [GND Clamp] keyword describes the I (current) and V (voltage) relationship when the input or output pad of a buffer is driven below ground (or the reference specified by the [GND Clamp Reference] keyword).For an I/O buffer, this is the ground-relative data gathered while the buffer is in the high impedance state. Meanwhile, the [POWER Clamp] defines an I-V relationship when the input or output of a buffer is driven above Vcc (or the reference specified by the [POWER Clamp Reference] keyword).For an I/O buffer, this is the Vcc-relative data gathered while the buffer is in the high impedance state.Why does configuration fail on Agilex™ 7 FPGA Rev A Development Kits when using Quartus® Prime Pro Edition Software version 21.2?
Description Due to a problem with the Linear Voltage Regulators (LTM46XX) used on some of the Agilex™ 7 FPGA Rev A Development Kits, you may experience configuration failures when using Quartus® Prime Pro Edition Software v21.2. This failure occurs because the voltage required by Agilex™ 7 devices during configuration is higher than the voltage the LTM46XX Regulators are programmed to supply. You might see the following error messages during configuration: Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00800008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Linear Voltage Regulator using a Linear Technologies USB-to PMBus Controller and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following register values for the LTM46XX device: VOUT_MAX = 1.0V VOUT_OV_FAULT_LIMIT = 30% VOUT_OV_WARN_LIMIT = 30% Changing these values will configure the LTM46XX Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to configure successfully.What is the difference between USERCODE and UESCODE?
Description USERCODE is a Joint Test Action Group (JTAG) instruction defined in the IEEE 1149.1-1990 JTAG specification that allows you to program a 32-bit user electronic signature into the device during programming (typically for design version control). When the USERCODE instruction is loaded into the device, you can shift the signature out of the device. You can specify any 32-bit pattern in this signature. Although UESCODE is not defined in the JTAG specification, this instruction uses the JTAG state machine to shift a signature out of the device, thus providing the same version control capability as the USERCODE instruction. UESCODE can use one or more instructions to read a signature out of the device. Since UESCODE is an Altera ® instruction, you must use a Jam file (.jam) generated by the MAX PLUS ® II software to read out the instruction. You can set the USERCODE or UESCODEregister in the MAX PLUS II software via the User Code option (Assign menu -> Global Project Device Options). Table 1 lists the USERCODE or UESCODE register length for Altera devices. Table 1. USERCODE & UESCODE Register Lengths Device Instruction Length (bits) APEX ™ 20K USERCODE 32 FLEX ® 10K USERCODE 32 (1) FLEX 10KE USERCODE 32 (1) FLEX 8000 NA NA FLEX 6000 NA NA MAX ® 9000A UESCODE 16 MAX 7000A UESCODE 16 MAX 7000AE USERCODE 32 MAX 7000B USERCODE 32 MAX 3000A USERCODE 32 Configuration devices USERCODE 32 Note: (1) Seven bits determined by the user, 25 bits predetermined. For more information on USERCODE and UESCODE, refer to AN 39: IEEE 1149.1(JTAG) Boundary-Scan Testing in Altera Devices (PDF). Related Articles What is the state of Altera device I/O pins when reading the UESCODE instruction?Why does Active Serial (AS) configuration from a Macronix MX25L device fail in Stratix® V, Arria® V, and Cyclone® V devices when using AS programming?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.1, Active Serial (AS) configuration from a Macronix MX25L device fails in Stratix® V, Arria® V, and Cyclone® V devices when programming the MX25L device using AS programming with a programmer object file (.pof) for AS x4 mode. This is a known problem that is mentioned in the following knowledge article: Why does the active serial (AS) configuration fail in Intel® Stratix® V, Intel® Arria® V, and Intel® Cyclone® V device when using a 256Mbit or larger density of Macronix MX25L or Cypress S25FL-S device for configuration device? Although patch 0.05std for Intel Quartus Prime Standard Edition Software version 18.1 for the problem mentioned above is available from the following knowledge base article, it doesn't improve the problem when programming an MX25L device with a .pof for AS x4 mode: Why do Cypress* flash devices S25FL256 and S25FL512 not get programmed with Intel® Quartus® Prime Standard edition software version 18.1 when using Intel® Cyclone® 10 LP or legacy devices? Resolution Program a Macronix MX25L device using JIC programming with a JTAG indirect configuration (.jic) file with Intel® Quartus® Prime Standard Edition Software version 18.1 with patch 0.05std. This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 19.1. Related Articles www.intel.com/content/www/us/en/support/programmable/articles/000076446.html, www.intel.com/content/www/us/en/support/programmable/articles/000077034.htmlWhy does ASx4 configuration fail for Intel® Stratix® 10 devices when using OSC_CLK_1 as the configuration clock source?
Description Due to a known problem in Intel® Quartus® Prime Pro Edition software version 20.3 and earlier, ASx4 configuration of Intel® Stratix® 10 devices may fail intermittently when OSC_CLK_1 is used as configuration clock source. For all Intel® Stratix® 10 devices AS_CLK is 125MHz For Intel® Stratix® 10 GX040, Intel® Stratix® 10 SX040, and Intel® Stratix® 10 TX040 devices only, AS_CLK is 125MHz, or 133MHz Resolution As a workaround, avoid the combinations stated in the description. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.Arria10 CLKUSR pin IO standard and power
Description CLKUSR is defined as a configuration pin, and it is a dual purpose I/O pins( dual-purpose I/O pins (DATA[0:31],CLKUSR, INIT_DONE, DEV_OE, and DEV_CLRn)). When dual-purpose configuration pins are used for configuration, tie VCCIO of the bank to the same regulator as VCCPGM, ranging from 1.2V, 1.5V, or 1.8V. so VCCIO of CLKUSR should be the same as VCCPGM when CLKUSR as configuration .Error: Can't recognize silicon ID for device 1
Description You may be receiving this error if you have 2 programming headers (JTAG and Active Serial (AS)) on your board and are trying to program the EPCS device directly but are connected to the JTAG header. If you are directly programming the EPCS device you will need to make sure you have the programming cable connected to the AS programming header. You also may get this error if you have a noisy TCK signal or if the JTAG or AS header are not powered with the correct voltage. Related Articles Why do I get the error Can't recognize silicon ID for device in the Quartus II software when I try to program my enhanced configuration device with the ByteBlasterMV™ cable?Which Quartus II versions supports FLEX, APEX, ACEX, and HardCopy Stratix device families?
Description Design software support for FLEX, APEX, ACEX, and HardCopy Stratix device families is not provided in versions of the Quartus II software beginning with version 9.1. Use the Quartus II software version 9.0 or earlier to support those devices. Resolution Refer to the section Design Software Support for Mature Device Families in the Quartus II Software Device Support Release Notes (PDF) for the Quartus II software version 9.1 for details.Where can I get the FIT rate for Altera devices that are not stated in the Altera Reliability Report?
Description You should use the next higher density devices FIT rate for devices that are not stated in the Altera Reliability Report (PDF). The FIT rate is dependent on the technology process. Therefore, the FIT rate for Altera® devices within the same family with the same process technology will be very similar and can be used for devices not explicitly listed in the reliability report. Altera does not list the reliability data for all packages of each device family.