cc1plus.exe: out of memory allocating 65536 bytes
Description This error may be seen when compiling large software projects on Windows platforms. cc1plus.exe is a 32bit Windows application and has access to 2GB of memory on Windows. Resolution To work around this problem, Windows can be configured to allow 32bit applications access to a 3GB address space. 1. Enable 3GB address space for 32bit applications on Windows: From Windows command prompt run: bcdedit /set IncreaseUserVa 3072 2. Allow cc1plus.exe to use the larger address space From Windows command prompt run: editbin /LARGEADDRESSAWARE "<path>/cc1plus.exe“ This problem is scheduled to be fixed in a future release of the SoC EDS Software.What is the difference between USERCODE and UESCODE?
Description USERCODE is a Joint Test Action Group (JTAG) instruction defined in the IEEE 1149.1-1990 JTAG specification that allows you to program a 32-bit user electronic signature into the device during programming (typically for design version control). When the USERCODE instruction is loaded into the device, you can shift the signature out of the device. You can specify any 32-bit pattern in this signature. Although UESCODE is not defined in the JTAG specification, this instruction uses the JTAG state machine to shift a signature out of the device, thus providing the same version control capability as the USERCODE instruction. UESCODE can use one or more instructions to read a signature out of the device. Since UESCODE is an Altera ® instruction, you must use a Jam file (.jam) generated by the MAX PLUS ® II software to read out the instruction. You can set the USERCODE or UESCODEregister in the MAX PLUS II software via the User Code option (Assign menu -> Global Project Device Options). Table 1 lists the USERCODE or UESCODE register length for Altera devices. Table 1. USERCODE & UESCODE Register Lengths Device Instruction Length (bits) APEX ™ 20K USERCODE 32 FLEX ® 10K USERCODE 32 (1) FLEX 10KE USERCODE 32 (1) FLEX 8000 NA NA FLEX 6000 NA NA MAX ® 9000A UESCODE 16 MAX 7000A UESCODE 16 MAX 7000AE USERCODE 32 MAX 7000B USERCODE 32 MAX 3000A USERCODE 32 Configuration devices USERCODE 32 Note: (1) Seven bits determined by the user, 25 bits predetermined. For more information on USERCODE and UESCODE, refer to AN 39: IEEE 1149.1(JTAG) Boundary-Scan Testing in Altera Devices (PDF). Related Articles What is the state of Altera device I/O pins when reading the UESCODE instruction?Failed to launch MegaWizard™ Plug-In Manager. PLL Intel® FPGA IP v18.0 could not be found in the specified library paths
Description In the Quartus® Prime software version 18.0, when you want to open the MegaWizard™ for editing, you may see error message "Failed to launch MegaWizard™ Plug-In Manager. PLL Intel® FPGA IP v18.0 could not be found in the specified library paths". Resolution To work around this problem, 1) Locate the .lst file of the missing IP in your Intel® FPGA program directory. For example, for the missing PLL, locate "pll_wizard.lst". In the case of Windows: Windows <installation_directory> \ip\altera\altera_pll In the case of Linux: Linux <installation_directory>/linux64/ip/altera/altera_pll 2) Change the text. "<ALIAS>Altera® PLL v18.0</ALIAS>" to "<ALIAS>PLL Intel® FPGA IP v18.0</ALIAS>What do the [GND Clamp] and [POWER Clamp] keywords describe in an input/output buffer information specification (IBIS) model?
Description The [GND Clamp] keyword describes the I (current) and V (voltage) relationship when the input or output pad of a buffer is driven below ground (or the reference specified by the [GND Clamp Reference] keyword).For an I/O buffer, this is the ground-relative data gathered while the buffer is in the high impedance state. Meanwhile, the [POWER Clamp] defines an I-V relationship when the input or output of a buffer is driven above Vcc (or the reference specified by the [POWER Clamp Reference] keyword).For an I/O buffer, this is the Vcc-relative data gathered while the buffer is in the high impedance state.Why does Intel® Stratix® 10 EPE or QPA report lower DSP power when DSPs are instantiated in 27x27 mode?
Description Due to a problem in the EPE (Early Power Estimator) and QPA (Quartus Power Analyzer), you may see underestimated DSP power when DSPs are instantiated in 27x27 mode but the input numbers are 9 or 12 bits only. The 9x9 and 12x12 multipliers are handled properly in other DSP modes. Resolution To work around this problem, instantiate the DSPs in 18x18 mode when the input numbers are 9 or 12 bits as the QPA and EPE provide an accurate power estimation in 18x18 mode.Why the JAM files generated after compilation are not Real-Time ISP ready?
Description The Real-Time ISP compatible JAM file generation feature is not currently supported as part of the Quartus® Prime Software compilation flow. Resolution To automatically generate a JAM file compatible with the Real-Time ISP feature as part of the Quartus® Prime Software compilation flow, the Automatic Script Execution feature can be used. Follow the next steps to enable the generation of a Real-Time ISP compatible JAM file after the compilation process: 1. Create a TCL script on your project folder with the following line: qexec "quartus_cpf -c <output folder for project results>/<generated pof file> <jam file> -o background_programming=on" 2. Add the following line to your project QSF file: set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:<tcl script>" To verify that the process was successful, open the generated JAM file and look for the following keyword: DO_REAL_TIME_ISP. If this keyword is part of the generated JAM file, then the JAM file is Real-Time ISP ready.How do I program an EPCS device with a SOF file and Nios® II ELF file using the Quartus® II Programmer?
Description The steps needed to generate an EPCS programming file are as follows: Open the Nios II Command Shell (Nios II SDK Shell for pre-6.0 versions) Create a flash file from a SOF using the following command: sof2flash --epcs --input=<sof file name>.sof --output=<flash output file name>.flash --verbose Create a flash file from the ELF using the following command: elf2flash --epcs --base=0x0 --end=<end address> --after=<sof2flash output file name>.flash --input=<elf file name>.elf --output=<flash output file name>.flash Convert the ELF flash file from SREC to HEX nios2-elf-objcopy –input-target srec –output-target ihex <elf2flash output file name>.flash <Hex output file name>.hex The last step will generate a valid HEX file with the correct addressing for an EPCS device. You are now able to use the Quartus II SOF file and the newly created HEX file to create an EPCS programming file. To do this, in Quartus II go to the File menu and choose Convert Programming Files. NOTE: From within the Convert Programming Files window, if you receive an error indicating that the EPCS device does not have enough space for the file then select compression for the SOF file.Error: Can't recognize silicon ID for device 1
Description You may be receiving this error if you have 2 programming headers (JTAG and Active Serial (AS)) on your board and are trying to program the EPCS device directly but are connected to the JTAG header. If you are directly programming the EPCS device you will need to make sure you have the programming cable connected to the AS programming header. You also may get this error if you have a noisy TCK signal or if the JTAG or AS header are not powered with the correct voltage. Related Articles Why do I get the error Can't recognize silicon ID for device in the Quartus II software when I try to program my enhanced configuration device with the ByteBlasterMV™ cable?Why does configuration fail on Agilex™ 7 FPGA Rev A Development Kits when using Quartus® Prime Pro Edition Software version 21.2?
Description Due to a problem with the Linear Voltage Regulators (LTM46XX) used on some of the Agilex™ 7 FPGA Rev A Development Kits, you may experience configuration failures when using Quartus® Prime Pro Edition Software v21.2. This failure occurs because the voltage required by Agilex™ 7 devices during configuration is higher than the voltage the LTM46XX Regulators are programmed to supply. You might see the following error messages during configuration: Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00800008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Linear Voltage Regulator using a Linear Technologies USB-to PMBus Controller and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following register values for the LTM46XX device: VOUT_MAX = 1.0V VOUT_OV_FAULT_LIMIT = 30% VOUT_OV_WARN_LIMIT = 30% Changing these values will configure the LTM46XX Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to configure successfully.Why does .jic file programming of EPCQ-A devices fail when multiple Intel® Cyclone® 10 LP devices are in the same JTAG chain?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.1, the programming of EPCQ-A devices is executed incorrectly with JTAG Indirect Configuration (.jic) file. You will see the failure when there are more than three Intel® Cyclone® 10 LP devices in a single JTAG chain, where each is connected to an EPCQ-A device as configuration flash. Resolution This problem was fixed in a recent version of the Intel® Quartus® Prime Software.