cc1plus.exe: out of memory allocating 65536 bytes
Description This error may be seen when compiling large software projects on Windows platforms. cc1plus.exe is a 32bit Windows application and has access to 2GB of memory on Windows. Resolution To work around this problem, Windows can be configured to allow 32bit applications access to a 3GB address space. 1. Enable 3GB address space for 32bit applications on Windows: From Windows command prompt run: bcdedit /set IncreaseUserVa 3072 2. Allow cc1plus.exe to use the larger address space From Windows command prompt run: editbin /LARGEADDRESSAWARE "<path>/cc1plus.exe“ This problem is scheduled to be fixed in a future release of the SoC EDS Software.Why does configuration fail on Agilex™ 7 FPGA Rev A Development Kits when using Quartus® Prime Pro Edition Software version 21.2?
Description Due to a problem with the Linear Voltage Regulators (LTM46XX) used on some of the Agilex™ 7 FPGA Rev A Development Kits, you may experience configuration failures when using Quartus® Prime Pro Edition Software v21.2. This failure occurs because the voltage required by Agilex™ 7 devices during configuration is higher than the voltage the LTM46XX Regulators are programmed to supply. You might see the following error messages during configuration: Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00800008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Linear Voltage Regulator using a Linear Technologies USB-to PMBus Controller and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following register values for the LTM46XX device: VOUT_MAX = 1.0V VOUT_OV_FAULT_LIMIT = 30% VOUT_OV_WARN_LIMIT = 30% Changing these values will configure the LTM46XX Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to configure successfully.What do the [GND Clamp] and [POWER Clamp] keywords describe in an input/output buffer information specification (IBIS) model?
Description The [GND Clamp] keyword describes the I (current) and V (voltage) relationship when the input or output pad of a buffer is driven below ground (or the reference specified by the [GND Clamp Reference] keyword).For an I/O buffer, this is the ground-relative data gathered while the buffer is in the high impedance state. Meanwhile, the [POWER Clamp] defines an I-V relationship when the input or output of a buffer is driven above Vcc (or the reference specified by the [POWER Clamp Reference] keyword).For an I/O buffer, this is the Vcc-relative data gathered while the buffer is in the high impedance state.What is the difference between USERCODE and UESCODE?
Description USERCODE is a Joint Test Action Group (JTAG) instruction defined in the IEEE 1149.1-1990 JTAG specification that allows you to program a 32-bit user electronic signature into the device during programming (typically for design version control). When the USERCODE instruction is loaded into the device, you can shift the signature out of the device. You can specify any 32-bit pattern in this signature. Although UESCODE is not defined in the JTAG specification, this instruction uses the JTAG state machine to shift a signature out of the device, thus providing the same version control capability as the USERCODE instruction. UESCODE can use one or more instructions to read a signature out of the device. Since UESCODE is an Altera ® instruction, you must use a Jam file (.jam) generated by the MAX PLUS ® II software to read out the instruction. You can set the USERCODE or UESCODEregister in the MAX PLUS II software via the User Code option (Assign menu -> Global Project Device Options). Table 1 lists the USERCODE or UESCODE register length for Altera devices. Table 1. USERCODE & UESCODE Register Lengths Device Instruction Length (bits) APEX ™ 20K USERCODE 32 FLEX ® 10K USERCODE 32 (1) FLEX 10KE USERCODE 32 (1) FLEX 8000 NA NA FLEX 6000 NA NA MAX ® 9000A UESCODE 16 MAX 7000A UESCODE 16 MAX 7000AE USERCODE 32 MAX 7000B USERCODE 32 MAX 3000A USERCODE 32 Configuration devices USERCODE 32 Note: (1) Seven bits determined by the user, 25 bits predetermined. For more information on USERCODE and UESCODE, refer to AN 39: IEEE 1149.1(JTAG) Boundary-Scan Testing in Altera Devices (PDF). Related Articles What is the state of Altera device I/O pins when reading the UESCODE instruction?How do I program an EPCS device with a SOF file and Nios® II ELF file using the Quartus® II Programmer?
Description The steps needed to generate an EPCS programming file are as follows: Open the Nios II Command Shell (Nios II SDK Shell for pre-6.0 versions) Create a flash file from a SOF using the following command: sof2flash --epcs --input=<sof file name>.sof --output=<flash output file name>.flash --verbose Create a flash file from the ELF using the following command: elf2flash --epcs --base=0x0 --end=<end address> --after=<sof2flash output file name>.flash --input=<elf file name>.elf --output=<flash output file name>.flash Convert the ELF flash file from SREC to HEX nios2-elf-objcopy –input-target srec –output-target ihex <elf2flash output file name>.flash <Hex output file name>.hex The last step will generate a valid HEX file with the correct addressing for an EPCS device. You are now able to use the Quartus II SOF file and the newly created HEX file to create an EPCS programming file. To do this, in Quartus II go to the File menu and choose Convert Programming Files. NOTE: From within the Convert Programming Files window, if you receive an error indicating that the EPCS device does not have enough space for the file then select compression for the SOF file.Why can't the Parallel Flash Loader II Intel® FPGA IP configure Intel® Stratix® 10 devices?
Description The Paraller Flash Loader II Intel® FPGA IP (PFLII IP) will first check if CONF_DONE is low. The IP will not proceed with configuration if it is already high. This is why the PFLII IP cannot configure Intel® Stratix® 10 devices. Resolution Check if CONF_DONE is pulled up as CONF_DONE and INIT_DONE are no longer required to be pulled up to VCCIO_SDM. Note that SDMIO_0 and SDM_16 are initially pulled down. Hence an intermediate voltage level by pull-up and internal pull-down resister might cause configuration failure when using the PFLII IP. PFLII IP monitors CONF_DONE signal low as start condition of operation. This requirement has been changed for Intel® Stratix® 10 devices.How can the Convert Programming Files utility be executed during compilation in the Quartus II software?
Description Using the following procedure, you can automatically execute the Convert Programming Files utility during compilation in the Quartus® II software. Open Convert Programming Files... under the File menu Set your desired Convert Programming File settings Save Conversion Setup File (.cof) Create a .tcl file with following description qexec "quartus_cpf -c <conversion setup file>.cof" Add POST_FLOW_SCRIPT_FILE assignment to the Quartus II setup file (.qsf) set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:<tcl file>.tcl" Click Start Compilation under the Processing menu to execute full compilation When using POST_FLOW_SCRIPT_FILE, Post Configuration Processing is displayed in Status window during full compilation.Failed to launch MegaWizard™ Plug-In Manager. PLL Intel® FPGA IP v18.0 could not be found in the specified library paths
Description In the Quartus® Prime software version 18.0, when you want to open the MegaWizard™ for editing, you may see error message "Failed to launch MegaWizard™ Plug-In Manager. PLL Intel® FPGA IP v18.0 could not be found in the specified library paths". Resolution To work around this problem, 1) Locate the .lst file of the missing IP in your Intel® FPGA program directory. For example, for the missing PLL, locate "pll_wizard.lst". In the case of Windows: Windows <installation_directory> \ip\altera\altera_pll In the case of Linux: Linux <installation_directory>/linux64/ip/altera/altera_pll 2) Change the text. "<ALIAS>Altera® PLL v18.0</ALIAS>" to "<ALIAS>PLL Intel® FPGA IP v18.0</ALIAS>Which Quartus II versions supports FLEX, APEX, ACEX, and HardCopy Stratix device families?
Description Design software support for FLEX, APEX, ACEX, and HardCopy Stratix device families is not provided in versions of the Quartus II software beginning with version 9.1. Use the Quartus II software version 9.0 or earlier to support those devices. Resolution Refer to the section Design Software Support for Mature Device Families in the Quartus II Software Device Support Release Notes (PDF) for the Quartus II software version 9.1 for details.How can I monitor the RY/BY pin of the AM29LV128 flash device on the Nios® development board, Stratix® II Edition from within my Stratix II application?
Description In order to use the RY/BY output of the flash device within a design running on the Nios development board, Stratix II Edition follow the instructions below: Add an input pin to the config_controller design located in the <Nios II install directory>\examples\<HDL>\<development board>\EPM7128_flash_config_controller directory. Assign the new input pin to location 35 on the EPM7128 device. Recompile the design in the Quartus ® II tool. The EPM7128 device will now tri-state its connection to the flash's RY/BY pin. Program the EPM7128 device on the Stratix II board with the POF file generated in the above step. Open the Quartus II design which you are targeting to the Stratix II board. Go to the Assignment Editor and add the "Weak Pull-up Resistor" option for the RY/BY pin. After performing the above steps you can access the RY/BY output of the flash in your Stratix II design.