Why does configuration fail on Agilex™ 7 FPGA Rev A Development Kits when using Quartus® Prime Pro Edition Software version 21.2?
Description Due to a problem with the Linear Voltage Regulators (LTM46XX) used on some of the Agilex™ 7 FPGA Rev A Development Kits, you may experience configuration failures when using Quartus® Prime Pro Edition Software v21.2. This failure occurs because the voltage required by Agilex™ 7 devices during configuration is higher than the voltage the LTM46XX Regulators are programmed to supply. You might see the following error messages during configuration: Error(18948): Error message received from device: External hardware access error. (Subcode 0x0032, Info 0x00800008, Location 0x00001800) Error(22248): Detected a PMBUS error during configuration. Potential errors: VID setting is incorrect in the Quartus Prime project. The target device fails to communicate to a smart regulator or PMBUS master on a board. Resolution To solve this problem, you will need to reconfigure the Non-Volatile Memory registers of the Linear Voltage Regulator using a Linear Technologies USB-to PMBus Controller and the Linear Technologies LTpowerPlay Software. Using the PMBus Controller and the LTpowerPlay software, configure the following register values for the LTM46XX device: VOUT_MAX = 1.0V VOUT_OV_FAULT_LIMIT = 30% VOUT_OV_WARN_LIMIT = 30% Changing these values will configure the LTM46XX Voltage Regulator to operate within the required voltage range and allow the Agilex™ 7 device to configure successfully.Fatal Error: Read data comes back but dynamic OCT ctrl is not in read mode
Description You may see the following error when you simulate the UniPHY based DDR3 controller in full calibration mode. # ** Fatal: Read data comes back but dynamic OCT ctrl is not in read mode Resolution Open the following file in your simulation file-set: altdq_dqs2_ddio_3reg_<user_device>.sv Find the following line: (1, "Read data comes back but dynamic OCT ctrl is not in read mode"); Replace the line above with the following line: ("Read data comes back but dynamic OCT ctrl is not in read mode at time %f", ); The simulation should run without any errors once the above change is implemented.Is the hard transceiver 8B/10B encoder/decoder in Stratix, Arria, and Cyclone family transceiver devices Fibre Channel compliant?
Description No, the 8B/10B encoder/decoder does not satisfy all the requirements for the Fibre Channel protocol in Stratix® GX, Stratix II GX, Stratix IV GX/T, Arria® GX, Arria II GX, or Cyclone® IV GX devices. 1) Fibre Channel protocol requirements for 1.062 and 2.125 Gbps states that the transmitter needs to start up with negative running disparity. Further, the standard has disparity rules for Ordered Sets. -The embedded 8B/10B encoder does start up with negative disparity. However, the encoder does not contain the functionality to force negative current running disparity at any time. This is required to be able to meet the disparity rules for Ordered Sets. 2) Fibre Channel protocol requirements for "Detection of Invalid transmission Word" for 1.062 and 2.125 Gbps state that Ordered Sets received with incorrect beginning running disparity be flagged as an error. -The current 8B/10B implementation determines running disparity on a character-by-character basis and not Ordered Sets. Due to these non-compliances, customers may or may not be able to use the embedded 8B/10B encoder/decoder in the transceiver megafunction. This decision would have to be based on how the customer is implementing their Fibre Channel or Fibre Channel-like architecture. Possible workarounds: User would have to implement 8B/10B encoding and decoding blocks in the PLD core to be able to meet the specific requirements in both the transmit and receive directions. User could use 8B10B Encoder/Decoder MegaCore Function from Altera Corporation User could use Multi-Gigabit Fibre Channel Transport Core from MorethanIP References: Fibre Channel, Physical Signaling Interface (FC-PH) REV 2.13 December 4, 1991 Fibre Channel Framing and Signaling (FC-FS) REV 1.90Why do I get the error “Error (176286): Found 2 SPI blocks in design” when using Serial Flash Loader Intel® FPGA IP and ASMI Parallel II Intel FPGA IP?
Description This error may be seen if Serial Flash Loader IP and ASMI Parallel II IP is used together in the same design. Both of Serial Flash Loader IP and ASMI Parallel II IP core require ASMI interface access. Therefore, by having both IPs in the same design would cause conflict during compilation as both IPs cannot access the ASMI block at the same time. Resolution To work around this problem, follow the steps below: Turn ON the “Share ASMI interface in the design” check box in Serial Flash Loader IP parameter. Turn ON the “Disable dedicated Active Serial Interface” check box in ASMI Parallel II IP parameter. Route ASMI signals from the ASMI Parallel II IP and connect to the Serial Flash Loader IP ASMI input/output port. Hence, both IPs should be able to share the single ASMI block within Serial Flash Loader IP.Why does JTAG Boundary Scan fail on Intel® Stratix® 10 devices?
Description You may notice a failure while performing JTAG Boundary Scan Test on Intel® Stratix® 10 devices with pre-configuration BSDL files. Resolution For Stratix 10 devices, the MISCCTRL instruction is required to enable the Boundary Scan circuitry. To enable this instruction, copy the following lines of code and save it as an SVF file. This SVF file needs to be run prior to executing boundary scan test. SIR 10 TDI (013); STATE IDLE; SDR 8 (01);How can I monitor the RY/BY pin of the AM29LV128 flash device on the Nios® development board, Stratix® II Edition from within my Stratix II application?
Description In order to use the RY/BY output of the flash device within a design running on the Nios development board, Stratix II Edition follow the instructions below: Add an input pin to the config_controller design located in the <Nios II install directory>\examples\<HDL>\<development board>\EPM7128_flash_config_controller directory. Assign the new input pin to location 35 on the EPM7128 device. Recompile the design in the Quartus ® II tool. The EPM7128 device will now tri-state its connection to the flash's RY/BY pin. Program the EPM7128 device on the Stratix II board with the POF file generated in the above step. Open the Quartus II design which you are targeting to the Stratix II board. Go to the Assignment Editor and add the "Weak Pull-up Resistor" option for the RY/BY pin. After performing the above steps you can access the RY/BY output of the flash in your Stratix II design.Why can't the Parallel Flash Loader II Intel® FPGA IP configure Intel® Stratix® 10 devices?
Description The Paraller Flash Loader II Intel® FPGA IP (PFLII IP) will first check if CONF_DONE is low. The IP will not proceed with configuration if it is already high. This is why the PFLII IP cannot configure Intel® Stratix® 10 devices. Resolution Check if CONF_DONE is pulled up as CONF_DONE and INIT_DONE are no longer required to be pulled up to VCCIO_SDM. Note that SDMIO_0 and SDM_16 are initially pulled down. Hence an intermediate voltage level by pull-up and internal pull-down resister might cause configuration failure when using the PFLII IP. PFLII IP monitors CONF_DONE signal low as start condition of operation. This requirement has been changed for Intel® Stratix® 10 devices.Why the package plan of Intel® Cyclone® 10 LP devices found in Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook mismatch with Intel® Cyclone® 10 LP Pin-Out Files?
Description The package plan of Intel ®Cyclone® 10 LP devices is an initial release. Users should refer to the Pin-Out Files for Intel ®FPGA Devices webpage for the up-to-date version.Why does Matlab crash with DSP Builder version 12.0 SP1?
Description Due to a problem in the installer for the Quartus® II software version 12.0 SP1, Matlab may crash with an error message similar to: AppName: matlab.exe AppVer: 7.13.0.0 ModName: msvcr90.dll ModVer: 9.0.30729.6161 Offset: 0006ccd5 Resolution A patch is available to fix this problem for the Quartus II software version 12.0 SP1. See the related solution below titled Why do my IP functions not reflect updates for the Quartus II software version 12.0 SP1? to download and install this patch. This problem is fixed beginning with the Quartus II software version 12.0 SP2. Related Articles Why do my IP functions not reflect updates for the Quartus II software version 12.0 SP1? Why does Matlab crash when I try to generate a design using Altera’s DSP Builder blockset?