Why does Ashling* RiscFree* IDE for Altera* FPGA software reports unresolved inclusion warnings, despite a successful build of Nios® V processor software project?
Description Due to a problem in multiple versions of Ashling* RiscFree* IDE for Altera® FPGA, the unresolved inclusion warning might occur for any Nios ® V processor software projects. Note that, the warning is harmless. The affected software project will still build successfully. This is caused by a bug in the Indexer of Ashling* RiscFree* IDE, which fails to search for the relevant project files. The affected Ashling* RiscFree* IDE for Altera FPGA are: Software version v25.1.1 (dated as 31 st Jan 2025) Software version v25.2.1 (dated as 9 th May 2025) Software version v25.3.1 (dated 1 st August 2025) Resolution This problem is currently scheduled to be resolved in future release of Ashling* RiscFree* IDE for Altera FPGA software version v26.1.0 (dated as 19 th Dec 2025). Meanwhile, you may safely ignore this warning, as it does not affect the functionality of your project. If needed, please refer to the related article for the recommended workaround. Related Article: Ahsling RiscFree IDE 25.1.1: Unresolved inclusion | Altera CommunityError: Unknown option: -port_type while execute set_instance_assignment with the option
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3, you might see this error when running a "set_instance_assignment" with -port_type option e.g. Error:Unknown option: -port_type Error:--------------------------------------------------------------------------- Error:Usage: set_instance_assignment [-h] [-help] [-long_help] [-comment <comment>] [-disable] [-entity <entity_name>] [-fall] [-from <source>] -name <name> [-remove] [-rise] [-section_id <section id>] [-tag <data>] [-to <destination>] [<value>] Error: -h: Quick usage Error: -help: Short help Error: -long_help: Long help with examples and possible return values Error: -comment <comment>: Comment Error: -disable: Option to disable assignment Error: -entity <entity_name>: Entity to which to add assignment Error: -fall: Option applies to falling edge Error: -from <source>: Source of assignment Error: -name <name>: Assignment name Error: -remove: Option to remove assignment Error: -rise: Option applies to rising edge Error: -section_id <section id>: Section id Error: -tag <data>: Option to tag data to this assignment Error: -to <destination>: Destination of assignment Error: <value>: Assignment value Error:--------------------------------------------------------------------------- Error: while executing Error:"set_instance_assignment -name DUPLICATE_SYNC_FANIN …" Resolution A patch is available to fix this problem in the Quartus® Prime Pro Edition Software version 25.3. Download and install patch 0.24 below This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Error: invalid command name "else"
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see the error messages below when generating a VHDL simulation model in Platform Designer that includes the Remote Update IP. Error: invalid command name "else" Info: while executing Info: "else { Info: do_vhdl_sim_cbx altera_remote_update_core Info: }" Info: (procedure "do_vhdl_sim" line 8) Info: invoked from within Info: "do_vhdl_sim altera_remote_update_core" Error: Generation stopped, 1 or more modules remaining Resolution To work around this problem, generate Verilog Simulation Model for Remote Update IP. This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. Related IP Remote Update IPWhy does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem, choose one of the following options: Use Quartus® Prime Standard Edition Software version 24.1 or earlier to instantiate the ALTPLL IP. Then either: i. Upgrade the Quartus® project to version 25.1, or ii. Copy the wizard-generated HDL file from the ALTPLL IP and add it to the Quartus® project in version 25.1. Use a Linux* operating system. This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why do I unexpectedly observe intermittent DDM Errors?
Description Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus® Prime Pro Edition software, Quartus Embedded Edition software or select standalone tools may cause the software or tool to crash with an error similar to the crash signature shown below. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and v25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. Crash Signature: Error (22912): Unhandled exception: Fatal Error: Assertion failed tools/cpp/ddm/ddm_assessor.cpp:53: DDM_T::verify_token(token) : Cannot identify the client from function assertion_error in tools/cpp/ddm_report/ddm_report_msg.cpp@465 *** Fatal Error: Program termination requested *** *** Below is the stack trace at the time the error occurred. *** The lines beginning "Err Handler" represent frames relating *** to generating this report. *** The point at which the error occurred is somewhere after these lines. *** There may be a few frames representing standard/library code *** before the Quartus frames begin. *** The search for the error should begin with the Quartus frames. *** Unwinder: libunwind *** Stack depth: 15 Quartus 0x24e67: err_terminator() + 0x1bc (ccl_err) Quartus 0xb036a: __cxxabiv1::__terminate(void (*)()) + 0xa (stdc++) Quartus 0xb03d5: (stdc++) Quartus 0xb0628: (stdc++) Quartus 0x1680d: void ddm_throw<DDM_RUNTIME_ERROR>(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x26d (ddm_report) Quartus 0x13fae: DDM_REPORT::DDM_ASSERTION_HANDLER::assertion_error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) const + 0xde (ddm_report) Quartus 0x12a52: DDM_REPORT::ASSERTION_HANDLER::error(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >) + 0x72 (ddm_report) Quartus 0x13e64: DDM_REPORT::detail::assert_at_line(char const*, char const*, int, char const*, ...) + 0x1b4 (ddm_report) Quartus 0x205fb0: ddm_set_lassessor(DDM_T_ASSESSOR*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x60 (ddm) Quartus 0xf4445: DMS_MANAGER::DMS_MANAGER() + 0x5c5 (dni_dms) Quartus 0xf45b2: DMS_MANAGER::get() + 0x7a (dni_dms) Quartus 0xf6db4: _GLOBAL__sub_I_dms_manager.cpp + 0x58 (dni_dms) Quartus 0x647e: (ld-linux-x86-64) Quartus 0x6568: (ld-linux-x86-64) Quartus 0x202ca: (ld-linux-x86-64) Resolution To work around this problem: For Windows machines Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Double click on the executable ending in “windows.exe”. When the GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch is installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Windows, use the following command: <patch_filename.exe> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: quartus-25.3-0.27-windows.exe --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer For Linux machines: Download and unzip the Quartus Prime Pro version zip file that matches your Quartus Prime Pro version from this KDB. Ensure you run chmod +x on the file ending with linux.run. Run in the command line: ./<installation_patch_run_file>. When GUI pops up, press Next. Note that the GUI may look slightly different depending on the version of Quartus you are using. Accept the license agreement Specify the directory where the patch needs to be applied which may be a different location than Quartus install if you have standalone tools in a different directory from your Quartus Prime Pro software installation. Keep “Allow Patch to be uninstalled” selected. Select the software in which to install the patch: The patch will install in the directory of the software or tool you have selected. You will see an uninstall directory for the patch in your software or tool folder where patch installed; it will contain an executable to uninstall the patch if required for any reason. To confirm patch is installed, you can run ./quartus_sh -v or corresponding version command for your tool via command line. Alternatively, you can Open Quartus in the GUI and select Help → About Quartus Prime in the main menu. If you are opening up a standalone tool you will navigate to Help-> About <tool_name>. For the Command Line Implementation of the patch in Linux, use the following command: ./<patch_filename.run> --mode unattended --installdir <your_install_directory> --accept_eula 1 --patch_to [quartus|qprogrammer|qemb|pta] # An example to patch Quartus Prime Pro Edition v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 # An example to patch the Standalone Programmer for Quartus Prime Pro Software v25.3: ./quartus-25.3-0.27-linux.run --mode unattended --installdir /tmp/altera_pro/25.3 --accept_eula 1 --patch_to qprogrammer This issue is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software. The below table lists the patches that are available and the associated patch number. The patch zip files are attached to the KDB below: Quartus Prime Pro Edition Version Patch Number 23.3 0.52 23.4 0.70 23.4.1 1.01 24.1 0.52 24.2 0.64 24.3 0.35 24.3.1 1.29 25.1 0.36 25.1.1 1.31 25.3 0.27 25.3.1 1.02Why does the SPI (4 Wire Serial) IP report hold violations in Timing Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see hold timing violations during Timing Analyzer when using the SPI (4 Wire Serial) IP. The SPI IP generates an SDC file that includes the following incorrect constraint: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This constraint can cause hold timing violations between the spi_gen_clk and the external clock, making timing closure difficult—especially in designs with multiple SPI instances. This problem does not occur in the Quartus® Prime Standard Edition Software, where such an SDC constraint is not generated for the SPI IP. Resolution To work around this problem: Remove the incorrect constraint from the IP-generated SDC file: Delete the following line: create_generated_clock -name spi_gen_clk -divide_by {4} -source [get_pins $ipath|tx_holding_primed|clk] [get_pins $ipath|SCLK_reg|q] This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.Internal Error: Sub-system: QPR, File: /quartus/comp/qpr/qpr_route_mask_generator_details.h, Line: 594
Description Due to a problem in Quartus® Prime Pro Edition Software versions 25.1 and 25.1.1, you might see this internal error at the fitter stage when compiling a Partial Reconfiguration (PR) implementation that uses a global reset on fast input/output registers. The base revision compiles successfully, the error occurs only in PR implementations with this global reset usage. Resolution To work around this problem in the Quartus® Prime Pro Edition Software v25.1.1 or v25.1, download and install the patches below. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.1.Error(24244): Found an error when generating the IBIS Output File for board analysis
Description Due to a problem is Quartus® Prime Pro Edition Software version 25.3, you might see this error when generating this IBIS files. This problem only occurs on Windows* OS. This problem occurs because the quartus_py.exe file has changed location in the installation directory but the IBIS writer still calls the file from the previous location. Resolution To work around this problem, copy the file quartus_py.exe from this directory \altera_pro\25.3\qcore\bin64\quartus_py.exe to this one \altera_pro\25.3\quartus\bin64\quartus_py.exe This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IP
