Why does the DisplayPort IP design example fail to generate a programming file when using the Quartus® Prime Pro Edition Software v19.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software v19.1, designs that use the Nios® II/e processor core without a valid Nios® II processor license will fail to generate programming files even though the design compilation is successful. The DisplayPort IP design example uses the Nios II/e processor core. Hence, it will be impacted by this problem. Resolution To work around this problem in the Quartus® Prime Pro Edition Software v19.1, install the patch 0.02 below and regenerate the DisplayPort IP design example: This problem is fixed starting with the Quartus Prime Pro Edition Software v19.2.
Internal Error: Sub-system: RDB, File: /quartus/db/rdb/rdb_utility.cpp, Line: 1944 rval == nullptr
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see this internal error when performing an IP Upgrade. Resolution To work around this problem, delete the qdb folder before compiling the project. This problem is scheduled to be fixed in a future version of the Quartus® Prime Pro Edition Software.Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why is there no video data coming from TX source when using the HDMI Intel® Arria® 10 FPGA IP Design Example with Bitec HDMI daughter card revision 6?
Description Due to an incorrect assignment in the HDMI Intel® Arria 10 FPGA IP Design Example, HDMI IP does not work with the Bitec HDMI daughter card revision 4 and revision 6. Resolution To work around this problem, replace project directory/rtl/hdmi_rx/hdmi_rx_top.v with hdmi-rx-top.v Support for the Bitec HDMI daughter card revision 4 and revision 6 cards are removed starting with the Intel® Quartus® Prime Pro Edition Software version 21.2.How to run Arria® 10 SoCFPGA-HardwareLib-Ethernet-A10-ARMCC example in SoC FPGA Embedded Development Suite (SoC EDS) Professional Edition Software Version 2020.1?
Description Due to a problem in running directly the Arria® 10 SoCFPGA-HardwareLib-Ethernet-A10-ARMCC example in SoC FPGA Embedded Development Suite (SoC EDS) Professional Edition Software Version 2020.1. The application hung after printing the below lines in the App console, and the Arria® 10 SX SoC Development Kit is not getting any IP address from the Server. Resolution To workaround this problem, please find attached document SoCFPGA-HardwareLib-Ethernet-A10-ARMCC.pdf to follow the step by step procedure to run the Arria® 10 SoCFPGA-HardwareLib-Ethernet-A10-ARMCC example.add_instance: Component intel_niosv_m_unit version <x.y> is not installed - loaded latest installed version <x.y> instead. Please check for parameter mismatches.
Description Platform Designer may show an “add_instance” warning message from the Nios® V Processor Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition Software v21.4 when, Instantiating the Nios® V Processor Intel® FPGA IP. Performing an IP Upgrade on the same IP from software version 21.3 to 21.4. This is due to a mismatch with the IP version number in the Intel Quartus Prime Software. The full warning message reads as: add_instance: Component intel_niosv_m_unit version 21.1.0 is not installed - loaded latest installed version 21.1.1 instead. Please check for parameter mismatches. Resolution To work around this problem, download and install the patch for the Intel® Quartus® Prime Pro Edition Software v21.4. Download and install Patch for version 21.4 from the following links: Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 for Windows (.exe) Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 for Linux (.run) Readme for Intel Quartus Prime Pro Software v21.4 Solution Patch 0.13 (.txt)Why does a design with a TX and RX Soft-CDR LVDS SERDES assigned to the same bank in an Intel® Arria® 10 device fail to fit?
Description Due to a bug in the Quartus® II software, a design that has LVDS SERDES IP core configured in TX mode and RX Soft-CDR mode assigned to the same I/O bank in an Intel® Arria® 10 device will fail at the fitter stage. This is because the phase-locked loop (PLL) instances within the two IP cores will not be correctly merged by the Quartus® II software. Therefore different PLLs will be required for the different LVDS SERDES IP cores. Each I/O bank has only one I/O PLL though. This problem only affects the RX Soft-CDR configuration. RX Non-DPA or RX DPA-FIFO configurations are not affected. Note that the Triple Speed Ethernet IP core uses LVDS SERDES IP configured in RX Soft-CDR mode. Resolution Download the following patch for version 14.0 Intel Arria 10 FPGA Edition of the Quartus® II software: Version 14.0a10 patch 0.01a for Windows (.exe) Version 14.0a10 patch 0.01a for Linux (.run) Version 14.0a10 patch 0.01a readme file (.txt) This problem is fixed starting with the Quartus® II software version 14.1.Error: dse: couldn't load library "..\22.1\quartus\dspba\backend\windows64\dspip_recipes.dll":
Description Due to a problem in the Intel® Quartus® Prime® Pro Edition Software version 22.1 Windows version, you may see the below error when generating the Unified FFT Intel® FPGA IPs: Error: dse: couldn't load library "..\22.1\quartus\dspba\backend\windows64\dspip_recipes.dll": invalid argument while executing "__altera__safe_load {C:\intelFPGA_pro\22.1\quartus\dspba\backend\windows64\dspip_recipes.dll}" ("uplevel" body line 1) invoked from within "uplevel 1 [list __altera__safe_load {*}$args]" (procedure "load" line 2) invoked from within "load $path_to_lib " (procedure "load_dsdk_wrapper" line 8) invoked from within "load_dsdk_wrapper" (procedure "call_dsdk" line 3) invoked from within "call_dsdk "none" "." "report" $freq" (procedure "elaboration_callback" line 67) invoked from within "elaboration_callback" Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 22.1 Windows version. Download and install Patch 0.16 from the attachment below. Download the patch Intel® Quartus® Prime Pro Edition version 22.1 Patch 0.16 for Windows (.exe) Download the Readme for Intel® Quartus® Prime Pro Edition version 22.1 Patch 0.16 (.txt)Why does it take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and Standard Edition software version 21.1 and earlier, it might take a long time until the SDI II Intel® FPGA IP Receiver detects video standard when receiving SD-SDI video standard. This problem might occur when the clock sources of the rx_coreclk and the xcvr_refclk in the SDI II Intel FPGA IP are 0 ppm tolerance. Resolution A patch is available to fix this problem for the Intel® Quartus® Prime Standard Edition Software version 18.1. Download and install patch 0.23std from the appropriate link below, then re-generate your programming file. Download patch 0.23std for Windows (Quartus-18.1std-0.23std-windows.exe) Download patch 0.23std for Linux (Quartus-18.1std-0.23std-linux.run) Download the Readme for patch 0.23std (Quartus-18.1std-0.23std-readme.txt) This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro/Standard Edition Software.Intel® Arria® 10 SoC HPS I2C not functioning in the latest u-boot-socfpga-v2021.04 for Intel® Arria® 10 SoC FPGA when enabling I2C using GHRD
Description Due to a problem in the u-boot-socfpga-v2021.04 for Intel® Arria® 10 SoC FPGA, U-boot hang after enabling I2C in "./configs". After enabling the I2C in u-boot-socfpga-v2021.04 for Intel® Arria® 10 SoC FPGA, you might encounter error when booting the kernel, "Starting kernel …". Resolution A patch is available to fix this problem. Download and install patch 0002-debug-i2c-kernel-fix.patch.
