AI Suite - How to interpret these graphs in Model Analyzer GUI
Hello Altera Community What can I learn from these subgraphs? I'm not sure how to connect it to the dla layer device file. The compiler told me: [ INFO ] The input graph is split into 9 subgraph(s), FPGA:3 CPU:6. (unsupported_layer_chains.dot) There are 9 nodes with "Transpose does not precede an FC layer." and 2 nodes with "Interpolation input not in NCDHW layout" (hetero_subgraphs_TensorFlow_Frontend_IR_3.dot) Why is there a node for device subgraph? Thanks in advance.How does the FPGA AI Suite utilize Agilex 5 DSP Blocks?
Hello Altera Community. I have a module called "dot_bf16" that uses the bf16 floating point format to calculate dot product and I am wondering if it uses the Agilex5 AI optimized DSP blocks to do this. I can't myself see how the DSP blocks are configured because they are all encrypted. 1. Agilex™ 5 Variable Precision DSP Blocks Overview • Variable Precision DSP Blocks User Guide Agilex™ 5 FPGAs and SoCs • Altera Documentation and Resources Center This document states that there are 3 operational modes for tensor mode: 1. Tensor float point mode 2. Tensor fixed point mode 3. Tensor accumulation mode Does the FPGA AI Suite utilize any of these? I also noticed the module uses a FSM and controller.
AI Suite - Spatial IP outputs wrong value
Hello Altera Community When looking at my Spatial IP in Signal Tap, I can see that it outputs a wrong value. Please help me identify where this mistakes happen. Below is the Signal Tap result of my test: 3D903C90 - 3D9C3D87 -BD983E38 However from my golden_output_sink_port_0.txt I'm expecting this value: 3D12BC8D - 3DA43E1E - 3DABBE18 Below is the Singal Tap of my input I'm inserting the values I got from input_vlogkw.txt from the DLA_COMPILER. Here is a list of warnings I got from Quartus, but they are from proteced sv files that I can't acess: Warning(16761): VHDL warning at spatial_first.vhd(146): actual for formal port "reset_reset" is neither a static name nor a globally static expression Warning(13469): Verilog HDL assignment warning at dot_core_controller.sv(381): truncated value with size 6 to match size of target (5) Warning(16788): Net "out[0][31]" does not have a driver at dsp_sum_of_2n_bf16xbf16.sv(118) Warning(13469): Verilog HDL assignment warning at dot_core_controller.sv(381): truncated value with size 6 to match size of target (5) Warning(21620): Design Assistant Results: 1 of 1 High severity rules issued violations in snapshot 'partitioned'. Please refer to DRC report 'C:/Users/mads/Desktop/test/quartus/output_files/spatial_first.drc.partitioned.rpt' for more information Warning(25315): Some pins are missing drive strength (current strength), termination and/or slew rate assignments. Refer to the I/O Assignment Warnings report for details. Warning(332158): Clock uncertainty characteristics of the A5EB013BB23BE4SR1 device are preliminary Warning(18291): Timing characteristics of device A5EB013BB23BE4SR1 are preliminary Warning(332060): Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment. Warning(332158): Clock uncertainty characteristics of the A5EB013BB23BE4SR1 device are preliminary Warning(21620): Design Assistant Results: 3 of 34 High severity rules issued violations in snapshot 'final'. Please refer to DRC report 'C:/Users/mads/Desktop/test/quartus/output_files/spatial_first.tq.drc.signoff.rpt' for more information Attached is Netlist viewer of my Spatial IP.
