Why does fitter take a long time when a large number of protocol IP instances/profiles are used for GTS Dynamic Reconfiguration in the Quartus® Prime Pro Edition software versions 25.3.1 and earlier?
Description The fitter process may take significantly longer when many IP instances or profiles are used for Dynamic Reconfiguration in Quartus Prime Pro Edition software versions 25.3.1 and earlier. Depending on the number of IP profiles, the fitter may take several days to complete. Resolution The fitter process may take significantly longer when many IP instances or profiles are used for Dynamic Reconfiguration in Quartus Prime Pro Edition software version 25.3.1 and earlier. To overcome this problem, some of the precautions measured users will have to take to prevent this longer fitter runtime problem. Some steps are mentioned in section 7 point#6 of GTS Dynamic Reconfiguration Controller IP User Guide, version 25.3.1. Add SDC constraints for mutually exclusive IP variants into clock groups, although this is ultimately required. Identifying and constraining these exclusive clocks constraints before running the fitter can help avoid prolonged fitter runtimes. For example: set_clock_groups -physically_exclusive -group [get_clocks dr_top_inst|ip_variant_1_inst*|*] -group [get_clocks dr_top_inst|ip_variant_2_inst*|*] Add the following constraints in SDC can help avoid prolonged STA runtime for a large number of profiles. qsta_utility::disable_slower_multi_clocks Additional include the following line in the Dynamic Reconfiguration Quartus Project QSF file can significantly reduce fitter time for a large number of profiles. set_global_assignment name REMOVE_SLOWER_CLOCKS_DURING_FITTER ON Note: In your project .qsf file, ensure that the SDC_FILE QSF assignment is placed after the IP_FILE QSF assignments. Failure to do so results in a warning in the Quartus Prime Pro Edition software, and the SDC constraints are then ignored as mentioned in Article 343689. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.
Why are the HPS GMII to RGMII Adapter FPGA IP outputs always stuck to 0 on Agilex™ 5 designs?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the HPS GMII to RGMII Adapter FPGA IP is not functioning for designs targeting Agilex™ 5. You may observe HPS GMII to RGMII Adapter FPGA IP outputs are always stuck to 0 and/or PHY is not receiving any packet from FPGA IO. This problem occurs when HPS XGMAC is routed to FPGA IO using the HPS GMII to RGMII Adapter FPGA IP. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.19 from the following links: Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Windows (.exe) Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Linux (.run) Readme for Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 (.txt) The patches will enable HPS GMII to RGMII Adapter FPGA IP to perform basic network transmission at 10Mbps/100Mbps link rate. 1Gbps speed is not supported in this patch. Additionally, for Linux OS, you must modify the Linux Device Tree description in <linux-socfpga folder>/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts> to specify mac-mode as “gmii” for the EMAC instance being used with the FPGA IO pins. In the example below, the HPS gmac1 is selected for routing to FPGA IO: &gmac1 { status = "okay"; phy-mode = "rgmii-id"; mac-mode = "gmii"; phy-handle = <&emac1_phy0>; max-frame-size = <9000>; mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; emac1_phy0: ethernet-phy@0 { reg = <0>; }; }; }; This problem is scheduled to be fix in a future release of the Quartus® Prime Pro Edition Software. Additional Information Embedded Peripherals IP User Guide Updated for Quartus® Prime Design Suite: 24.1 Publication Content ID: 683130 Chapter: HPS GMII to RGMII Adapter Intel FPGA IPWhy does HPS GMII to RGMII Adapter FPGA IP have hold time violation on Agilex™ 5 designs?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the HPS GMII to RGMII Adapter IP timing analyzer will report hold timing violation for designs targeting Agilex™ 5 designs. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.19 from the following links: Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Windows (.exe) Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Linux (.run) Readme for Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 (.txt) This problem is scheduled to be fix in a future release of the Quartus® Prime Pro Edition Software.Why does External Memory Interface (EMIF) calibration fail on A5ED013BB23AE4/5/6SR0 devices when using Quartus® Prime Pro Edition Software version 24.2?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you might see EMIF calibration failure when targeting the following Agilex™ 5 devices. To enable the hardware support for External Memory Interfaces for the following OPNs in Quartus® Prime Pro Edition Software version 24.2, please install patch 0.09. A5ED013BB23AE4SR0 A5ED013BB23AE5SR0 A5ED013BB23AE6SR0 Resolution Download and install Patch 0.09 for the Quartus® Prime Pro Edition Software version 24.2. Then, generate the EMIF IP and compile the design after installing the patch Quartus® Prime Pro Edition Software v24.2 Patch 0.09. Quartus® Prime Pro Edition Software v24.2 Patch 0.09 for Windows (.exe) Quartus® Prime Pro Edition Software v24.2 Patch 0.09 for Linux (.run) Readme for Quartus® Prime Pro Edition Software v24.2 Patch 0.09 (.txt)Why does HPS EMAC MDIO not work when routed to FPGA IO on Agilex™ 5 designs?
Description Due to a problem in the Quartus™ Prime Pro Edition Software version 24.1, when routed to FPGA IO, the HPS EMAC MDIO does not work as expected for designs targeting Agilex™ 5 device. You will be able to route MDIO to FPGA IO in Platform Designer and generate the design without errors, but the actual input and output will always be 0. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1. Download and install Patch 0.19 from the following links: Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Windows (.exe) Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 for Linux (.run) Readme for Quartus™ Prime Pro Edition Software v24.1 Patch 0.19 (.txt) This problem has been fixed in a future release of the Quartus™ Prime Pro Edition software version 24.2 and later versions..Why do PCI Express links in the Agilex™ 5 E-Series devices fail link training after cold reset or fail to retrain after the reference clock to the transceiver TX PLL and CDR are resumed after a disruption?
Description To protect a transceiver reference clock buffer from aging and damage, it is turned off when there is no valid clock activity on the buffer. After the reference clock is brought up and stable at the buffer, users need to turn on the buffer by either reconfiguring the device or performing read and write operations to the reference clock buffer registers via the Avalon® Memory-Mapped interface. For PCIe links in Agilex™ 5 devices, the reference clock buffers are turned off if the reference clocks driving transceiver TX PLL and CDR are unavailable before device configuration starts or are disrupted during PCIe link operation. When the reference clock becomes available, the buffers remain turned off without users manually turning them on. Hence, the PCIe links fail to come up. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.3.1. Download and install Patch 1.02fw from the appropriate link below. Download patch 1.02fw for Windows Download patch 1.02fw for Linux Download the Readme for patch 1.02fw This problem will be fixed in a future release of the Quartus® Prime Pro Edition software. With this fix, reference clock buffers that are already off and turned on automatically when the reference clock is available.Why does the width of the pma_cu_clk port on the GTS JESD204B IP not match the width of the pma_cu_clk port on the GTS Reset Sequencer IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, when the number of lanes per converter device L parameter in the GTS JESD204B IP Parameter Editor is set to L = 6 or L = 8, the pma_cu_clk port has a width of 1 bit in the generated HDL code. However, for L = 6 or L = 8, the GTS Reset Sequencer IP necessitates a pma_cu_clk port width of 2 bits, which will cause a port width mismatch between the two ports. When using Platform Designer to connect the pma_cu_clk ports from the GTS Reset Sequencer IP to the GTS JESD204B IP, an error will be shown in the System Messages console: Error: jesd_gts_ss.jesd_gts_jesd204b.pma_cu_clk/jesd_gts_ss_intel_srcss_gts.o_pma_cu_clk: Signal clk has width 1 on jesd_gts_jesd204b.pma_cu_clk, but has width 2 on jesd_gts_ss_intel_srcss_gts.o_pma_cu_clk Resolution This workaround is only applicable during IP generation. 1. In the IP Files, open the <IP name>.v file at the Project Navigator: Eg: <IP name>/synth/<IP name>.v 2. Edit the pma_cu_clk width manually by adding one bit as shown below: 3. Save and close <IP name>.v file Altera® recommends installing the following patch in the Altera® Quartus® Prime Pro Edition Software version 24.3: Download patch 0.02 for Windows (quartus-24.3-0.02-windows.exe) Download patch 0.02 for Linux (quartus-24.3-0.02-linux.run) Download the Readme for patch 0.02 (quartus-24.3-0.02-readme.txt) After installing the patch, regenerate the GTS JESD204B IP via Platform Designer. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3.1.Why does the GTS HDMI FPGA IP Design Example fail on hardware?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3.1, the GTS HDMI FPGA IP Design Example fails to link after programming. This is due to the Input Reference Clock Buffer Protection enablement; the clock buffers are turned off before device configuration starts and never turned back on even when the reference clock becomes available. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.3.1. Download and install Patch 1.02fw from the following links: quartus-24.3.1-1.02fw-windows.exe quartus-24.3.1-1.02fw-linux.run Readme for version 24.3.1 Patch 1.02fw (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does EMIF for HPS LPDDR4 fail calibration on the Agilex™ 5 FPGA and SoC FPGA?
Description In the Quartus® Prime Pro Edition Software 24.3, when configuring the Agilex™ 5 FPGAs and SoC FPGAs with the EMIF for HPS IP and LPDDR4 device implemented as dual rank (2 chip selects), dual channels (i.e., 4 dies each being 16 Gbit in density), calibration can fail. Resolution Please download the Quartus® Prime Pro Edition Software 24.3 patch 0.11 for a fix. This issue is planned to be fixed in a later Quartus® Prime Pro Edition Software release. quartus-24.3-0.11-windows.exe quartus-24.3-0.11-linux.run quartus-24.3-0.11-readme.txtWhy do reading/writing registers via JTAG return garbage value while performing hardware testing of the design example for the Triple-Speed Ethernet FPGA IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, a hardcoded JTAG master value in the basic.tcl file causes the TCL script to override the user-selected JTAG master value, leading to incorrect/invalid register reads and writes, which results in garbage values. Resolution To work around this problem and ensure that the correct JTAG master selected by the user is used during register read and write operations, perform the following steps: Replace the file <design_example_dir>/hardware_test_design/hwtest/agx/2xtbi_pma/basic/basic.tcl with the new basic.tcl file from the attachment. Run the hardware testing for the design example using the modified script files. This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.
