Why does the F-Tile Ethernet Dynamic Reconfiguration (DR) design not work when one of the profiles has PTP enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 23.3, the F-Tile Ethernet designs using Dynamic Reconfiguration with PTP enabled on some of the profiles will fail to work correctly if the startup profile of the design does not have PTP enabled. Resolution To work around this problem, ensure that the startup profile of your dynamically reconfigurable Ethernet design has PTP enabled if any of the profiles have PTP enabled.
Why do FPGA GPIO interrupts fail to trigger in the HPS GSRD for the Agilex® 5 FPGA E-Series Premium Dev Kit in release 25.3.1?
Description Due to a problem in the 25.3.1 GHRD 2.0 (Baseline) for Agilex® 5 FPGA E-Series Premium Development Kit, the FPGA GPIO interrupts fail to trigger when the push buttons are pressed. The error message observed during the interrupts exercising is the following: root@agilex5e:~# modprobe gpio_interrupt gpio_number=592 ubtr_type 2 modeprobe: FATAL: Modeule gpio_interrupt not found in directory /lib/modules/6.12.43-altera-xyz root@agilex5e:~# modprobe gpio_interrupt gpio_number=524 ubtr_type 3 modeprobe: FATAL: Modeule gpio_interrupt not found in directory /lib/modules/6.12.43-altera-xyz The problem has been rooted caused to the PIO interrupt mapping in the GHRD, which incorrectly uses IRQ18 instead of IRQ17. Resolution To workaround this problem, you need to change the PIO interrupt mapping in the GHRD to use IRQ17 instead of IRQ18. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why is there a fitter failure when using reference clock from HVIO System PLL for FABRIC_USE_CASE in the Agilex™ 3/ Agilex™ 5 FPGA GTS System PLL Clocks IP?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, user will encounter fitter failure when they are using HVIO Reference Clock for Fabric_Use_Case. Resolution For a workaround, you need to set location assignment based on your selected devices in QSF assignment: Agilex™ 5 Family and Series Density Device Group Package Code Location Assignment A5E 013 A/B B23A/B32A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] A5E 028 A/B B23A/B23A/ M16A For Bank: 1A [SMHSSIPLLWRAP_X0_Y7_N1956] 1B [SMHSSIPLLWRAP_X0_Y54_N1956] 4A [SMHSSIPLLWRAP_X121_Y7_N1956] A5E 065 A/B B23A/B32A 1A: [SMHSSIPLLWRAP_X121_Y7_N1956] 1B: [SMHSSIPLLWRAP_X0_Y54_N1956] 1C: [SMHSSIPLLWRAP_X0_Y101_N1956] 4A: [SMHSSIPLLWRAP_X185_Y7_N1956] 4B [SMHSSIPLLWRAP_X185_Y54_N1956] 4C [SMHSSIPLLWRAP_X185_Y101_N1956] A5D 064 A/B B32A 1A [SMHSSIPLLWRAP_X0_Y7_N2406] 1B [SMHSSIPLLWRAP_X0_Y15_N2406] 1C [SMHSSIPLLWRAP_X0_Y99_N2406] 1D [SMHSSIPLLWRAP_X0_Y107_N2406] 4A [SMHSSIPLLWRAP_X159_Y7_N2406] 4B [SMHSSIPLLWRAP_X159_Y15_N2406] 4C [SMHSSIPLLWRAP_X159_Y99_N2406] 4D [SMHSSIPLLWRAP_X159_Y107_N2406] The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why is there a simulation failure when we are generating and running the Agilex ™ 5 FPGA Example Design 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence or 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence?
Description Due to a problem in the generated example design for 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence and 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence in Quartus® Prime Pro Edition software version 25.3.1, user will encounter failed simulation result. Resolution For a workaround, upon successfully generated example design, you need to follow the steps accordingly to resolve this problem. Step 1: you are required to go to the generated design example folder, which is: intel_directphy_gts_0_example_design/example_design/rtl_folder Step 2: Open the file top.sv, then make the modification to the reset_sequencer module, sss1 at line 542. Update the o_pma_cu_clk[0] --> o_pma_cu_clk [1:0] Step 3: Modify the pma_cu_clk[0] in line number 787 in the same file (top.sv) shown below from: i_pma_cu_clk(pma_cu_clk[0]) --> i_pma_cu_clk(pma_cu_clk[1:0]) Step 4: Rerun the compilation and simulation. The example design will be able to pass simulation. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1Why does the generation of one of the Example Designs for the GTS Dynamic Reconfiguration Controller IP fail on a Windows* machine using Quartus® Prime Pro Edition software version 25.3.1?
The Example Design COMBO (PTP/CPRI MR) was first released in Quartus® Prime Pro Edition software version 25.3.1, as noted in Table 3 of the GTS Dynamic Reconfiguration Controller IP User Guide. Users may encounter problems generating this example design on a Windows machine, which can result in an error as shown below and cause the example design generation to fail. Resolution (custom) There is no workaround to generate the GTS Dynamic Reconfiguration Controller IP [COMBO (PTP/CPRI MR)] example design using the Windows* version of Quartus Prime Pro Edition software. The only option is to use the Linux* version of Quartus Prime Pro Edition software to generate this example design. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Why does the fitter fail when a large number of protocol IP instances/profiles are used for GTS Dynamic Reconfiguration in the Quartus® Prime Pro Edition software versions 25.3.1 and earlier?
Description When using a large number of IP instances for GTS Dynamic Reconfiguration, a fitter failure may occur if the combined total of channels and any IP GTS PMA/FEC Direct IP instances or GTS CPRIPHY IP Instances exceeds 71 for Dynamic Reconfiguration in Quartus® Prime Pro Edition software versions 25.3.1 and earlier. This limitation is explicitly stated in section 5.1 of the GTS Dynamic Reconfiguration Controller IP User Guide version 25.3.1. Resolution There is no workaround available in Quartus Prime Pro Edition software versions 25.3 and earlier, but patch is available for Quartus Prime Pro Edition software version 25.3.1 Patch 1.15 corresponds to this problem. You can download and install version 25.3.1 patch 1.15 below. To prevent this problem, ensure that the maximum limit of 71 instances is not exceeded in your dynamic reconfiguration design, as specified in section 5.1 of the GTS Dynamic Reconfiguration Controller IP User Guide version 25.3.1. The problem has been fixed starting with Quartus® Prime Pro Edition software version 26.1.Error: Logic Generation failed to load results from Design Analysis and cannot get the list of IPs in the design
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 or earlier, you might see this error message during the Support-Logic Generation stage when compiling a design on the Windows* Operating System. This error occurs when Windows* long path support is disabled. Windows* limits the combined length of a file name and its path to 260 characters. If the project path exceeds this limit, the Quartus® Software cannot access required IP or design files. Resolution To work around this problem, enable Windows* long path support by updating the registry: a) Open Registry Editor: Press Windows Key + R, type regedit, and press Enter. b) Navigate to HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\FileSystem c) Find LongPathsEnabled. Double-click it and set "Value data" to 1. If the LongPathsEnabled doesn't exist, right-click, select New > DWORD (32-bit) Value, and name it LongPathsEnabled. d) Restart your computer. This error message will be enhanced in a future release of the Quartus ® Prime Pro Edition Software.Internal Error: Sub-system: U2B2_HVIO, File: /quartus/db/u2b2_hvio/u2b2_hvio_hviowr_translator_module.cpp
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, you might see this internal error during the Fitter stage for the Agilex™ 5 FPGA device. This problem occurs because the IO location for the design's IO port (and, more broadly, any IOs that support the 3.3-V LVCMOS IOSTD) cannot simultaneously drive both the local H/V(horizontal and vertical wires) clock network and the global clock network. This is due to shared mux settings and is a limitation of the Agilex™ 5 FPGA device. Resolution To work around this problem, use either one of the following assignments in the Quartus® Prime settings file (.qsf): set_instance_assignment -name GLOBAL_SIGNAL ON -to <port name> set_instance_assignment -name GLOBAL_SIGNAL OFF -to <port name> This will resolve the split between global and local fanout, ensuring that the IO drives either entirely global or entirely local routing. The choice between ON or OFF depends on your use case and the signal's timing requirements. You are best positioned to figure out your design intent. Local routing might be preferable if the signal is more delay-sensitive (for example, due to potential data fanout), especially since it's otherwise a relatively low-fanout signal. This problem has been fixed in version 25.3.1 for Quartus® Prime Pro Edition Software version.Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_traversal_manager.cpp, Line: 2769
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 to 25.3.1, you might see this internal error at the Fitter Finalize stage when the design contains combinational loops. Static Timing Analysis analyzes timing graphs without loops. When a combinational loop is detected, Timing Analyzer replaces the loop with bypass edges whose delays represent the longest path through the loop. When new timing corners are added later in the finalize stage, the bypass edge delays may not be computed for all corners, causing an internal consistency check to fail and resulting in an internal error. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.Why does my single rank DDR5 RDIMM design fail to compile after upgrading to Quartus® Prime Pro Edition Software version 26.1?
Description Starting with Quartus® Prime Pro Edition software version 26.1, the DDR5 DIMM External Memory Interfaces (EMIF) IP explicitly generates two chip select (CS) signals per sub‑channel for DDR5 RDIMMs in the HDL output, even when using single‑rank RDIMMs. This is required because DDR5 RDIMM calibration and RCD operations depend on the presence of both CS signals, regardless of the number of ranks. Enforcing the generation of both CS0 and CS1 ensures that these signals are properly routed from the FPGA to the DIMM connector and prevents cases where CS1 may be left unconnected on the PCB, which could result in initialization or calibration failures. After upgrading to this software version, compilation may fail if the existing top‑level design exposes only one CS pin per sub‑channel. Resolution To resolve this issue, update your top‑level design to expose two CS pins per sub‑channel and connect both signals to the DDR5 DIMM External Memory Interfaces (EMIF) IP in the project. Before: Verilog output wire [0:0] mem_0_cs_n, output wire [0:0] mem_1_cs_n, After: Verilog output wire [1:0] mem_0_cs_n, output wire [1:0] mem_1_cs_n,
