Why is there a simulation failure when we are generating and running the Agilex ™ 5 FPGA Example Design 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence or 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence?

Description

Due to a problem in the generated example design for 6x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence and 8x10.3125G PMA Direct (System PLL Clocking) with Custom Cadence in Quartus® Prime Pro Edition software version 25.3.1, user will encounter failed simulation result.

Resolution

For a workaround, upon successfully generated example design, you need to follow the steps accordingly to resolve this problem.

• Step 1: you are required to go to the generated design example folder, which is: intel_directphy_gts_0_example_design/example_design/rtl_folder 
• Step 2: Open the file top.sv, then make the modification to the reset_sequencer module, sss1 at line 542. Update the o_pma_cu_clk[0] --> o_pma_cu_clk [1:0] 

 

• Step 3: Modify the pma_cu_clk[0] in line number 787 in the same file (top.sv) shown below from:

 

i_pma_cu_clk(pma_cu_clk[0]) --> i_pma_cu_clk(pma_cu_clk[1:0])

• Step 4: Rerun the compilation and simulation. The example design will be able to pass simulation.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.