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When does the tRAMP timing begin for Cyclone 5 Power Supplies?
Hi All, I am currently designing a power supply setup for a Cyclone 5 FPGA. In the datasheet, it is stated that if power supplies do not reach operating conditions within the maximum tRAMP time allowed (100ms in my scenario with standard POR delay) the device will remain tri-stated. My question is, does the tRAMP spec apply to each different supply individually? Or, does it apply to each supply as a whole? e.g. Can I switch on the Vcc supply (ramps within say 10ms) and then wait a few seconds and switch on another supply? Or, must they all turn on within 100ms after the first supply begins to ramp? The image below is an extract from the datasheet, Figure 10-4 of the Cyclone V Handbook Volume 1, and seems to imply they can be timed individually?
Cyclone 10LP Power requirements
Hello, I am planning to use Cyclone 10LP (F484 BGA) with a 3.3V Active Serial configuration scheme. All Active Serial configuration pins are part of Bank 1. I hope to be able to use banks 5, 6 and 8 with 2.5V. However, those banks contains the MSEL, CONF_DONE, INIT_DONE, CRC_ERROR and parallel IO pins. I have been reading the Cyclone 10LP handbooks and guides, but it is still unclear exactly what is the powerup requirements. Handbook chapter 6.2.1 says: "After device power up, the device does not release nSTATUS until VCCINT, VCCA, and VCCIO (for I/O banks in which the configuration and JTAG pins reside) are above the POR trip point of the device. • VCCINT and VCCA are monitored for brown-out conditions after device power up. • VCCA is the analog power to the phase-locked loop (PLL)." The actual POR trip point is not defined anywhere that I can find (not in the device datasheet). Also, it is not clear which banks are involved. By selecting 3.3V Active Serial, is the banks mentioned (5, 6, 😎😎 😎locked to 3.3V, even if their IO are not part of the actual configuration? I appreciate any insight to this. Regards, Ivar Svendsen
Cyclone V GS power estimation
Hello All, I have a 10 years old project with Cyclone 3 and Quartus 10, and now I will migrate it to Cyclone V Gx with Quartus 21.1 with adding and removing few IPs. The Design is not finished yet, but I need to get to estimate the power consumption for different Rails. I ran the EPE sheet with CSV file from Quarts21 also I ran the power analyzer tool with Quartus21 My question is, the reported results show a VCCIO with 2.14mA. VCC 156mA, VCCAUS 69mA as in the figures below. However, the hardware designer saying this is very low power consumption and something is not right about the results, but I have no idea what should I do to check if my results are correct or wrong. Do the results below make sense? Or it is too low? How can I double-check the power consumption if my design is not ready? Can I find any power consumption reference for Cyclone V? Do you have any advice regarding this topic? The results as follows: Design report power consumption Rails power VCCIO IO banks current VCCPD IO banks current The EPE sheet results of Quartus CSV file as follows:
AGIB027R29A1E2VR3 programming issue due to PMBus
Hello, In our custom hardware we are using AGIB027R29A1E2VR3 device. while programming .sof we are getting following error. Error(18948): Error message received from device: External hardware access error. (Subcode 0xC80E, Info 0x00000047, Location 0x00001800) Error(22248): The first I2C command has failed, no response from Voltage Regulator. Verify the address used in Quartus project matches that of the Voltage Regulator, inspect the PMBus/I2C bus traffic, pull-ups, bus contention, etc. The 'info' field of this error contains the target I2C address. Error(209012): Operation failed When we check schematic we found PWRMGT_SCL and PWRMGT_SDA pins are not connected. As per documentation "When a –V or –E power option device is used, you must enable the SmartVID connection between the device and the VCC voltage regulator to allow the FPGA to directly control its core voltage requirements." as we are using -V device, as per intel PWRMGT_SCL and PWRMGT_SDA connection is mandatory. Please anyone can confirm FPGA programming failure is because of missing PMBus connection and if yes is there any way to bypass SmartVID feature(use -V device as -F which does not require SmartVID) any workaround for SmartVID feature. Thank You.
On-die capacitor and package parasitic for Cyclone V
Hello, I am looking for a model or file which has the value of on-die decoupling capacitors on power pins of the Cyclone V FPGA. I need this value of capacitor with ESR and ESL so as to correctly model the power pins for Power Integrity analysis of the board. Thanks in advance.
