Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you might see the following error when compiling Intel® Stratix® 10 designs containing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP: Fatal Error: Segment Violation: faulting address=0x8, PC=0x7f0d85c89714 : 0x7f0d85c89714: periph_fpp!FPP_CELL::add_link(FPP_LINK const&) + 0x4 This error might occur if the reference clocks for the HBM2 intellectual property (IP) are set as virtual pins. Resolution To work around this error, ensure that the reference clocks for the HBM2 IP do not have a virtual pin assignment. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.Error (175020): The Fitter cannot place logic IO_LANE that is part of Generic Component ed_synth_phylite_s20_0_example_design, to which it is constrained, because there are no valid locations in the region for logic of this type
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.4, you may encounter a fitter issue while placing REFCLK sharing between IO48 tiles within the same banks in PHY Lite Interfaces Intel Agilex® 7 FPGA IP. Resolution These errors are due to a hardware limitation. The fitter didn't check the REFCLK location constraint because it assumes the REFCLK needs to be in the same tile.Why does the EMIF Debug Toolkit report that the Stratix® 10 DDR4 CKE*, ODT*, and RESET signals are uncalibrated?
Description The EMIF Debug Toolkit doesn't deskew the Stratix® 10 DDR4 CKE* and ODT* signals directly because the DDR4 specification doesn't include them in the address/command parity calculation. Resolution In the Address / Command Margins section, the EMIF Debug Toolkit reports all the signals that could have a delay. Still, the margins are only reported on signals that are calibrated explicitly. However, the CKE*, ODT*, and RESET signals are calibrated implicitly based on the CS* level / deskew, and therefore, their margins aren't reported. The CKE*, ODT*, and RESET signals are programmed with the same delay setting value as the CS* signals. Note that the character * refers to the memory rank number.What is the pull-up resistor guideline for the DDR4 alert_n signal?
Description The recommendation is to start with a 10k ohm pull-up resistor to 1.2V for the DDR4 alert_n signal, and then the resistor can be adjusted to a different value as long as it meets the FPGA I/O buffer VIL and VIH specifications (refer to the FPGA device datasheet under the I/O Standards specification). Perform a board signal integrity simulation to verify the optimal setting.Why did the Timing report fail in the Agilex™ 7 FPGA M-Series External Memory Interface DDR4 DIMM Design Example?
Description The following Lockstep DDR4 DIMM configurations may be unable to meet timing requirements: DDR4 DIMM x64 DDR4 DIMM x64 + ECC DDR4 DIMM x72 Resolution Please constrain the user clock to a small region, or if possible, lower the operating frequency. If these workarounds do not solve the Timing violation, please reach out to your Altera sales representative for further assistance.Can the slew rate be changed in the EMIF IP for Intel Agilex® 7 FPGA devices?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.2 and earlier, the slew rate parameter in the EMIF IP for Intel Agilex® 7 FPGA devices cannot be changed. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.3.Error(18090): External memory and PHYLite interfaces must share a common clock and reset signals when constrained to the same I/O column.
Description Due to a problem in the Intel® Quartus® Prime software version 19.2 or earlier, you may see the fitter error message when you aren't sharing the same clock and reset signals across multiple Intel Arria® 10 EMIF IPs in the same I/O column. This message is incorrect, and you can follow the guidelines described in the Intel® Arria® 10 EMIF IP User Guide. To place multiple interfaces in the same I/O column, you must ensure that each interface's global reset signals (global_reset_n) come from the same input pin or signal. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.Why does the Intel® Arria® 10 DDR4 IP not correct an ECC error?
Resolution A correctable bit error will not be corrected in the Intel® Arria® 10 DDR4 IP when a data mask does not correspond to a full byte (for example, a 4-bit data mask). This is because the ECC logic can only support read-modify-write on a byte-wide basis.Why does the Intel® Stratix® 10 EMIF Toolkit report DQS Enable Calibration failure?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.3 and earlier, the Intel Stratix® EMIF Toolkit calibration report may show a DQS Enable Calibration failure even though both the DQ/DQS read and write margins show passing valid window values. This DQS Enable Calibration failure report can be ignored if the DQ/DQS read and write margins show passing valid window values. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 19.3 and earlier, you can also verify that the local_cal_success signal is asserted using the Signal Tap Logic Analyzer tool. This problem is fixed in the Intel Quartus Prime Pro Edition Software version 19.4 and later.Why does the EMIF Traffic Generator 2.0 become unresponsive when the burst length reaches or passes the end of the memory address space?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, you may see that the EMIF Traffic Generator 2.0 (TG2) does not assert the pass, fail, or timeout signals when the TG2 is set to sequential mode and the written address is within 127 address spaces to the end of the memory. For example, if the address 0xfff0 is written to with a burst length of 0x20, the TG2 will become unresponsive because this is an invalid command. Note: This problem does not occur when the TG2 is set to random mode or random-sequential mode because the address is generated to account for the size of the burst length. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.