Are there any functional or security updates for the Quartus® Prime Standard Edition Software version 23.1.1?
Description The Quartus® Prime Standard Edition Software version 23.1.1 Patch 1.01std includes functional and security updates. Users should keep their software up-to-date and follow the technical recommendations to help improve security. If you need additional security updates, they will be provided in this article as they become available. Resolution A patch is available to include this update for the Quartus® Prime Standard Edition Software version 23.1.1 and the Quartus® Prime Lite Edition Software Version 23.1.1. Download and install Patch 1.01std below. This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software and the Quartus® Prime Lite Edition Software.Quartus® Prime Pro Edition User Guide - Map file description not full in Table 3. Programming File Generator Output File Types
Description The description for the Map file is in Table 3. Programming File Generator Output File Types of the Quartus® Prime Pro Edition User Guide: Programmer is not full. User Guide: Quartus® Prime Pro Edition User Guide: Programmer ID: 683039 Version: 4/03/2023 Section: 2.2.1.2. Secondary Programming Files (Programming File Generator) Table: Programming File Generator Output File Types 2.2.1.2. Secondary Programming Files (Programming File Generator) Resolution Not full description is: A text file containing the byte addresses of pages and data stored in the memory of a configuration device for Full description should like below: A text file containing the byte addresses of pages and HEX data stored in the memory of an EPC4, EPC8, or EPC16 configuration device. The file stores the start and end addresses of the Main Block Data and Bottom Boot Data items, and the start and end addresses of pages within the Main Block Data item. This updated information will be added in the Intel® Quartus® Prime Pro Edition User Guide: Programmer, version 24.1.Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829Errors: 'MODULAR_ADC_0_DUAL_ADC_MODE' undeclared here (not in a function)
Description Due to a problem with the Quartus® Prime Standard Edition Software version 21.1, when Modular ADC Core IP used in a Nios® II Gen 2 system, you might see the following errors when building the Nios® II software project: 'MODULAR_ADC_0_DUAL_ADC_MODE' undeclared here (not in a function) 'MODULAR_ADC_0_IRQ_INTERRUPT_CONTROLLER_ID' undeclared here (first use in this function) 'MODULAR_ADC_0_IRQ' undeclared here (first use in this function) 'MODULAR_ADC_0_NAME' undeclared here (not in a function) Resolution To work around this problem, the altera_modular_adc.h file located in \intelFPGA\21.1\ip\altera\altera_modular_adc\top\HAL\inc needs to be replaced with a new one. Download the driver.zip file to obtain the updated altera_modular_adc.h file. This problem is scheduled to be fixed in the Quartus® Prime Standard Edition Software version 22.1 and later versions.
Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why I can't open Early Power Estimators (EPE) tool in the latest version of Microsoft Excel?
Description There is a compatibility issue with the current EPE tools with the latest update from Microsoft* on the Excel version 2505 and later. The update from Microsoft causes the EPE tools to stop working. Resolution There is no plan to fix this. Users need to use the Excel version before version 2505 for the EPE tools to work. There is a workaround if the user needs to use the latest Excel version, please contact Altera support and quote this ID #15018720346Where to get the MAX® 10 FPGA Variable Pitch Ball-Grid Array(VPBGA) 610-pin Package Information?
Description The MAX® 10 VPBGA 610-pin Package Information is not being listed in the FPGA Packaging Device Information. Resolution Download the MAX® 10 VPBGA 610-pin Package Information from the Altera® FPGA 04r-00549-00 Package Mechanical DrawingWhy does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 Lite
