How to reduce ROM/RAM requirements for a NIOSV Compact CPU Platform?
Hello ALTERA NIOSV Experts, I am trying to create a system in Quartus Platform Designer which has the following components: A 1G Tri mode ethernet IP (with 32 bit AVALON-ST TX/RX interfaces using minimum sized FIFOs) A RS 232 UART with no FIFO A couple of small FIFOs using AVALON-ST interfaces for data in and out of Platform via Conduits A NIOSV Compact CPU A JTAG UART ROM for NIOSV RAM for NIOSV My questions are about how to reduce the ROM (for the NIOSV compacts program) and RAM to the minimum amount. I am trying to shoehorn this all into a MAX10 FPGA ( Altera Max 10 part number 10M08SAU169I7G). When i build the BSP for this platform, with a "Hello World" program, it seems to need around 128 Bytes of ROM and several KBytes of RAM. Why is the program so large ? I expect it has to do with the BSP adding in drivers for all the Platform IP and it is getting bloated. What tactics are available for me to use in the Ashling RISC FREE IDE which i am using to create my BSP and/or Platform Designer to reduce the program size ? The FPGA i am trying to use only has around 48 K Bytes of RAM available in total ...so maybe this is not possible and i need a bigger FPGA of course ! Thanks for your help, Dr BarryCreated Free NIOSV IP evaluation license but did not get any license file by email?
Hi ALTERA NIOSV experts, I have created licenses (the free evaluation type) through the Intel Altera Licensing portal for NIOSV-c, NIOSV-g, and NIOSV-m IP types. I get 3 messages saying a license has been created and i can see all the correct fields are filled in on the license form each time. It then says you will get a license by email. But after 2 hours i still have not received anything from Intel-Altera. Is there a problem with this licensing platform ?Is there a time delay between creating a license and actually getting it by email ? Usually this occurs very quickly, but not in this case ! Any suggestions or help much appreciated ! Thanks, Barry
How to use SDRAM IP core on Agilex 3?
I am testing my project on Atum Nios V starter kit from terasic, which bases on Agilex 3 (A3CZ135BB18AE7S) and SDRAM(IS42VM32160G-6BLI). my purpose is, realize a Nios V system with RTOS and use the SDRAM as the program ram of the RTOS. My question: Agilex 3 is supported only by the higher version such as quartus pro 25.3, and the SDRAM ip is supported by previous old version quartus. do you have any solution that i can reuse the avalon interface SDRAM IP core on Agilex 3? thanks.
Ahsling RiscFree IDE 25.1.1: Unresolved inclusion
Hello, I'm making Nios V test project for Agilex 5 (Arrow AXE5000 Devkit), following instructions in AN 985 Nios V Processor Tutorial. It works basically, I can download and run Nios application on the target. Source window is marking all include files as "unresolved" although the project compiles fine. I can manually add links to all missing includes (most from /bsp/inc folders, some from riscfree/toolchain/riscv32-unknown-elf) to the app tree to resolve the issue. But apparently there's something wrong with the import Cmake project flow. Am I missing a step in the instructions? Regards Frank
Ashling RiscFree Nios V Error 2 and CMake Errors
Hello! I was building a Nios V/m systems to blink some LEDs. I am getting these errors I have followed the instructions from this forum post a few months ago: Ashling RiscV NiosV errors | Altera Community By setting the path variables I was able to get rid of some of the errors, but the ones pictured are still present. The program is able to run on the FPGA and does work correctly, so I think these errors might be a false error? I still would like to solve them. I am using Quartus V24.1-STD to generate the hardware, and Ashling RiscFree IDE V25.1.1, as well as the nios V shell. The BSP builds with no errors, it is the application that has the errors.
