Linux not Booting on custom Intel Cyclone V board
Hello, I was trying to build Linux file system from scratch for my custom Intel Cyclone V (5CSXFC6C6) board so I followed this (Embedded Linux Beginners Guide | Documentation | RocketBoards.org) guide. But it did not work out and I got a "Reset the board" error. I am using Ubuntu 18.04 and Quartus Prime Standard 18.1 edition. Then, I tried the same procedure on Arrow SoCkit Evaluation Board 5CSXFC6D6F31C6N. The guide was accurate till step 8 (I wrote the preloader and u-boot.img on sd card and it gave the same output and errors of zImage as suggested in the guide) but since “rel_socfpga-4.1_15.09.01_pr” release is no more available for linux-socfpga from Altera, I had to opt for a newer version of linux-socfpga. Now, newer versions of linux-socfpga do not support compilation using old “gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux” as suggested in the beginners guide, so I had to opt for a newer “gcc-linaro-6.5.0-2018.12-x86_64_arm-linux-gnueabihf”. I further used “socfpga-5.15.50-lts” as the new and stable version of linux-socfpga for cyclone-v and buildroot to build the image but it also didn’t work out and u-boot output threw errors for commands like "fatload" command not used properly and "echo $fpgadata" was empty). I tried another way (Building Bootloader for Cyclone V and Arria 10 | Documentation | RocketBoards.org 1) with Quartus 19.1 but it failed at bitbake step. It gave 2 errors after downloading 5+ GBs of data. I am stuck with this for more than 2 months. Can anyone suggest a better way to build things for my custom board from scratch? All the guides available are specific to some software or hardware and none of them have resulted working linux kernel for me. Note- Arrow SoCkit works fine when I load prebuilt image, which means all the hardware, sd card and switches are set correctly.
Autostart NIOS from external SDRAM problem
So my NIOS code has outgrown the available on chip RAM and I've moved it to off chip SDRAM. Very slow, but I fire up Eclipse and I can get it to run. I need to get it to run automatically and I've found snippets of information by perusing the NIOSII software developers Handbook but can anyone point me to definitive documentation. I know I need to persuade the compiler to produce a ROM image that becomes a MIF, which I believe it does, and get something (maybe a bootloader) to do the initialisation, and somewhere I need to tell the tools to run that code. Can anyone help with the blanks?
Kernel restart issue while trying to read or write from the address space of hps2fpga and lwhps2fpga
Currently working on a Arria 10 FPGA and faced this issue while trying to access the gpio connected on the lwhps to fpga bridge but when i try to access the lwhps2fpgs address section(0xff200000) my kernel stucks and restarts. below i have mentioned the bridge device tree fpga-bridge@ff200000 { compatible = “altr,socfpga-lwhps2fpga-bridge”; reg = <0xff200000 0x00200000>; resets = <0x06 0x61>; clocks = <0x08>; bridge-enable = <0x01>; altr,l3-syscon = <0x99>; phandle = <0x5b>; init_val = <1>; }; fpga-bridge@c0000000 { compatible = “altr,socfpga-hps2fpga-bridge”; reg = <0xc0000000 0x3c000000>; resets = <0x06 0x60>; clocks = <0x08>; bridge-enable = <0x01>; altr,l3-syscon = <0x99>; phandle = <0x5c>; init_val = <1>; }; been following this guide from rocket board: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 and also can any one please share the correct device tree for fpga2hps and fpgs2sdram bridge device tree node
Remote update for Cyclone 10GX
I am writing a bootloader programme using the Intel Remote update IP on a cyclone 10GX. The Remote update block is part of a NIOS II system and is setup using platform designer. The factory image is based at 0x20 in flash The application image is at 0x01001000 in flash From the factory I can successfully start the application image - all seems ok The application image will be stopped and the factory image restarted if there is a problem (e.g no WDT kicking), this also seems to work ok too. I can read back why the factory image has been restarted. However when in the application image there appears to be no way of telling that the application image is the image running. ie the RU_CONFIGURATION_MODE is 0 not 1 as I expect. This was set to 1, in the factory image, prior to starting the application image - using Altera's function "altera_remote_update_trigger_reconfig" I am correct in a saying that this register should be 1, to show the application image is being run? The user guide seems to suggest this is the case.
Remote system update for arria10 FPGA
Hi, we are using Arria 10 FPGA DEVICE "10AX057N2F40E2SG", we needed to use Remote system update feature for our custom board. From the intel design store, there are two reference design modules. But from rocketboards website it is stated as https://www.rocketboards.org/foswiki/Documentation/RemoteSystemUpdateCompatibility "The Remote System Update (RSU) is a feature available for Stratix 10 and Agilex FPGA devices" please Clarify whether Arria10 will support or NO! Thanks, Rajesh
