ARMDS cannot see source code in debugger
Hello I have an ARMDS_IDE debugger that works on Cyclone V EVB, I compiled PRELOADER and UBOOT using Quartus 18.1 and trying to debug the preloader code until reaching the UBOOT script processing. (ELF) Unfortunately, the Intel/Altera part seems to be fine. Cyclone V identifies the HPS as the first element in the JTAG chain (USB BLASTER), The CPU halts and its registers and memory can be seen through the ARMDS IDE. The CPU can be reset and controlled by the JTAG connection and the ARMDS, the JTAG clock speed is 16M. Unfortunately, the source code (C and H) cannot be seen as expected. Switching Toolchains and locating the corresponding folders in "Debug Options" setting, did not help. I will appreciate if anyone could assist in this issue, so it will be possible to use source level debugging. ARMDS2020.1 and 2024.1 shows the same behavior. Thank you in advance Joseph G.
Unable to run make file on ALtera SOC EDS
Im not able to complite the makefile and main.c file to make a executable file, I'm trying to execute the project on DE1soc hps linux, Im trying compile my_first_hps project. $ ls main.c Makefile girid@LAPTOP-T0N0O46H ~/OneDrive/Documents/3875/my_first_hps $ make arm-linux-gnueabihf-gcc -g -Wall -Dsoc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/ -c main.c -o main.o process_begin: CreateProcess(NULL, arm-linux-gnueabihf-gcc -g -Wall -Dsoc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/ -c main.c -o main.o, ...) failed. make (e=2): The system cannot find the file specified. make: *** [main.o] Error 2 girid@LAPTOP-T0N0O46H ~/OneDrive/Documents/3875/my_first_hps $ echo $SOCEDS_DEST_ROOT C:/intelFPGA/20.1/embedded girid@LAPTOP-T0N0O46H ~/OneDrive/Documents/3875/my_first_hps $ make arm-linux-gnueabihf-gcc -g -Wall -Dsoc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/ -c main.c -o main.o process_begin: CreateProcess(NULL, arm-linux-gnueabihf-gcc -g -Wall -Dsoc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av -IC:/intelFPGA/20.1/embedded/ip/altera/hps/altera_hps/hwlib/include/ -c main.c -o main.o, ...) failed. make (e=2): The system cannot find the file specified. make: *** [main.o] Error 2 girid@LAPTOP-T0N0O46H ~/OneDrive/Documents/3875/my_first_hps $ Make file: # TARGET = my_first_hps ALT_DEVICE_FAMILY ?= soc_cv_av SOCEDS_ROOT ?= $(SOCEDS_DEST_ROOT) HWLIBS_ROOT = $(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib CROSS_COMPILE = arm-linux-gnueabihf- CFLAGS = -g -Wall -D$(ALT_DEVICE_FAMILY) -I$(HWLIBS_ROOT)/include/$(ALT_DEVICE_FAMILY) -I$(HWLIBS_ROOT)/include/ LDFLAGS = -g -Wall CC = $(CROSS_COMPILE)gcc ARCH= arm build: $(TARGET) $(TARGET): main.o $(CC) $(LDFLAGS) $^ -o $@ %.o : %.c $(CC) $(CFLAGS) -c $< -o $@ .PHONY: clean clean: rm -f $(TARGET) *.a *.o *
Error using arm-eabi to make
Hi I'm using CycloneVsoc Dev Kit with QSPI boot. I've made a spl and the application image to boot. I found that the SPL can't find my application. So I tried another HelloWorld image. It works well. When I checked the objdump I found the format of the axf files are different. Here is the HelloWorld objdump: using arm-none-eabi tool chain And here is my project: using arm-eabi tool chain <downloaded with the SOC EDS> I also made a Timer Example, the format is the same as the HelloWorld one. I use the same linker file and the same flags, I don't know why it is different. Could you help me for that? I attached the Makefile I made and the source code.You may need to delete the gpio led part of the code. Best Wish Alex
de1-soc linux kernel moudle Makefile
hii i am using the de1-soc board and i want to load a simple "hello world " kernel driver that prints hello world on the kernel in the Makefile we need to specify the path to the directory of the source files of the kernel , how can i find this path i downloaded the console ver of the de1-soc from terasic website and it booting from a sd card and working fine or i be glad to get a Makefile that is tested to compile device driver for altera cyclone v hps of the de1-soc board i be glad for help thanks
SoC EDS Professional Version Shell fails to launch?
I've followed the guide on how to install the Intel SoC EDS Professional version, the Cygwin64 terminal, ARM DS and the MiniGW suite of tools. However when I go to launch the shell, it quickly terminates. The Cygwin64 terminal works. Why is it terminating? I have version 20.1 installed with Quartus Prime Pro version 23.3
Can't execute an ARM Compiler 5/6 built image from Arria V SoC devkit SDRAM without debugger
Hi, I try to build a bare metal app for the Arria V SoC devkit using Arm Compiler 6/5 (DS-5 built in) and load it from the QSPI into the SDRAM (on the devkit without debugger). The app is never executed. I followed several guides, All resulted with working preloader that doesn't load the app: 1. Link: https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/scatter-file-linker-script-and-preloader-integrations-for/m-p/1472491/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExHME5POUsyNERNRFVVfDE0NzI0OTF8U1VCU0NSSVBUSU9OU3xoSw#M1882 2. asdf soc hands baremetal (attached) 3. guide found in this forum (attached) 1 | My Environment - Windows 10 - SoC EDS 18.1.0.625 - DS-5 Ultimate Edition, Version: 5.29.1 (installed with SoC EDS) - Quartus Prime 18.1 (including Quartus Prime Programmer) 2 | Example Projects For comparison I used two example projects: 1. Altera-SoCFPGA-HardwareLib-Unhosted-AV-GNU - Link: (attached to this post) - Result: The built app is loaded successfully with debugger and without it (SoC only) 2. Altera-SoCFPGA-HardwareLib-Timer-AV-ARMCC - Link: (attached to this post) - Result: The app is loaded only when using debugger. I wish to load it without debugger. 3 | 1. I used the Arria V SoC GHRD handoff folder to build the preloader: - Checked SDRAM scrub - Unchecked watchdog interrupt and any boot device other than the QSPI - Next image address is 0x60000) I see the preloader UART prints. I use the same preloader with both images (only the GCC built image is executed without debugger) 2. In both cases I flash the bare metal app into the QSPI starting from address 0x60000: quartus_hps -c 1 -o PV -a 0x60000 [image_name].bin 3. I don’t know if its matters, but in project (2.1) the resulted ELF is converted to .bin using objcopy. In project (2.2) its converted using fromelf. In both cases I use the same mkimage command: mkimage -A arm -T standalone -C none -a [SDRAM_START_ADDR] -e 0 -n "baremetal_image" -d [name].bin [image_name].bin 4. The [SDRAM_START_ADDR] is different in both projects. In (2.2) its provided in the scatter file, in (2.1) its provided in the linker script. I did noticed a comment in the GCC project (2.1) linker script: MEMORY { boot_rom (rx) : ORIGIN = 0xfffd0000, LENGTH = 64K oc_ram (rwx) : ORIGIN = 0xffff0000, LENGTH = 64K /* Need to have 64bytes available before start of program, to store the mkimage header */ ram (rwx) : ORIGIN = 0x100000 + 0x40, LENGTH = 1023M - 0x40 } "Need to have 64bytes available before start of program, to store the mkimage header" I'm not sure this space exists in project (2.2) as well. Could this be the reason for my problem? 5. I looked at each project built ELF "Image entry point". In both cases it points to a valid place (proj 2.1 – cs3_reset , proj 2.2 – alt_interrupt_vector). Both lead to main So I don't know what is the specific difference causing the GCC project (2.1) built image to be loaded and work properly as opposed to the ARM project (2.2) built image.COT BOM-2, Request for part status information
Hello Intel Team, We are unable to find the part status of below mentioned MPN. Please provide us the current part status (Active, NRND, EOL or Obsolete) and Availability. So we would like to know the below information for the mentioned part, it is really appreciated if you could help us with the details. PEF22552EV1.1-G IC,DUAL E1/T1/J1 LINE INT,PPG-LBGA-160-1 EP4CE55F23I8LN IC,FPGA,EP4CE55,324I/O,CYCLON-IV,FBGA-484 EPCS4SI8N IC,FLASH,4Mb,SERIAL,SOIC-8 EP4CE6E22I7N IC,FPGA,EP4CE6,91 I/O,6272 LE,EQFP-144 EP2C70F672I8N IC,FPGA,EP2C70,422I/O,CYCLON II,FBGA-672 5M570ZF256I5N IC,FPGA,5M570Z,MAX V,FBGA-256 946587 IC,DUAL E1/T1/J1 LINE INT,PPG-LBGA-160-1 PEF22552EV11 IC,DUAL E1/T1/J1 LINE INT,PPG-LBGA-160-1 EPCQ4ASI8N IC,FLASH,4Mb,SERIAL,SOIC-8 EPCS4SI8N IC,FLASH,4Mb,SERIAL,SOIC-8 EP4CE6E22I7N IC,FPGA,EP4CE6,91 I/O,6272 LE,EQFP-144 EP2C70F672I8N IC,FPGA,EP2C70,422I/O,CYCLON II,FBGA-672 5M570ZF256I5N IC,FPGA,5M570Z,MAX V,FBGA-256 Thanks and Regards, Bireshwar B Beladhadi Component Engineer PH:+91 9742490090 Cyient | www.cyient.com |email: Bireshwarb.beladhadi@cyient.com
