Board Debug

4 Topics

Cyclone V build flow questions (from Quartus to U-boot)
Dear Intel and All, I am writing series of question and letting FAE or staff to settle. Q1: It is unclear that do previous version "hps_isw_handoff" can be reused on latest "https://github.com/altera-fpga/u-boot-socfpga". via the python script "cv_bsp_generator.py" Q2: Based on Q1, do any format in xml is updated or changed and introduce possible information lost? Q3: Experiment shows the HPS section via Q1 flow can generate a proper bootable result to distro on branch "socfpga_v2024.07". Where "socfpga_v2025.04" introduce immediate stuck on boot MMC1 message. Any bug and how to fix? Q4: Based on Q1 to Q3, using the old build flow on 18.1+bsp-editor no issues are found to communicate between HPS2FPGA or FPGA2HPS, FPGA2SDRAM or SDRAM2FPGA etc. Confirmed rbf is loaded and functioning. This is confirmed via HPS IIC to FPGA fabric. Where IIC devices are able to communicate under distro i2cdetect etc. However, using the cross-version flow the entire memory bridge h2f, f2h, lwh2f are all dead. Which unable to communicate properly. How to fix this? Q5: Under investigation, why the default dts on u-boot do not have 0xff200000 lwh2f bridge? These are the question pool we are having trouble. Please FAEs or stuffs response ASAP Thank You
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BrianSune_Froum
3 months ago Place SoC System
995Views
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Custom board on Cyclone V HPS SDRAM preloader test
Dear Intel and all, Apart from the DDR3 topology. The first stage testing shows a very puzzling behavior. BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock 50000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 600 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 488 KHz CLOCK: QSPI clock 2343 KHz RESET: COLD INFO : Watchdog enabled SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB SDRAM: Ensuring specified SDRAM size is correct ...failed
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BrianSune_Froum
4 months ago Place SoC System
4.1KViews
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DE2-35 send .hex image to PC through USB port
Hi guys! I'm doing an image processing project using the DE2-35 kit. So I have the image file in ".hex" format and I my workflow is: Load the ".hex" image (300KB) into the SRAM of the DE2-35 kit (512KB), and the MCU will access the SRAM to process the image (grayscale to be specific). After finishing processing the image, it will move the processed image to the USB port to transfer the image to my PC for display. I've successfully loaded the ".hex" image to the SRAM (It's a pain because there is only 512KB of SRAM) My questions are: 1. How do I process the image? 2. How do I move the processed image to the USB port for data transfer? 3. Is there a better way to transfer the processed image to my PC and how can I do it?
tuanquang97
6 months ago Place SoC System
592Views
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3Comments
Handoff Files Agilex V
Hi, I am using Quartus 24.1 with the Agilex V device (A5ED065BB32AE4SR0), and want to make some edits to the device tree so that I can blink some led's via linux cmd. My research so far has led me to read a lot's of rocketboard posts, posts in the forums here, and more. From what I can tell, after I conect the Platform Designer and generate HDL, then Compile in Quartus - I should be given a handoff/ folder with some files in it, and with this it should be possible to generate a preloader. Later I would then be able to edit the device tree for my the leds. If so - why is the only file/folder generated by this process referencing `handoff` the `hps_bootloader_handoff.bin` file? Many thanks! K
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K606
7 months ago Place SoC System
887Views
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3Comments