Why does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> This problem is scheduled to be fixed, beginning with the Ashling* RiscFree* IDE for Altera software version 25.3.1 (version dated 1 st August 2025).Why does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?
Description Due to a problem in the Quartus ® Prime Standard Edition software version 25.1, Nios ® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design. This problem affects: All Altera ® FPGA device families in Quartus ® Prime Standard Edition software, and All Nios ® V processor variants (Nios ® V/g, Nios ® V/m, and Nios ® V/c processors). It is because the generation of the Nios ® V processor VHDL testbench system is not supported in Quartus ® Prime Standard Edition software version 25.1. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition software. Related Articles 3.3.1. Preparing Hardware Design for Simulation
error: Unexpected use of HDL library function(s) (possibly due to taking the address of the function)!
Description You may see this error message when the Intel® FPGA SDK for OpenCL™ compiler executes an EFI(Extensible Firmware Interface) function which is equivalent to its OpenCL funtion Resolution This problem is fixed beginning with the Intel FPGA SDK for OpenCL compiler software version 18.1.Why does aocl diagnose fail while using Windows 10?
Description When using Windows® 10, aocl diagnose may fail even though the board is installed in the PC and the user has installed the drivers using aocl install. If the user has installed the drivers then opens Windows Device Manager, the board should show up under "unknown device". Why does this happen? Windows 10 enforces driver signatures by default and the OpenCL drivers for our development kits are not "signed" for Windows 10. Resolution To work around this problem, run aocl uninstall then reboot the computer. After the computer has restarted, disable Windows 10 signed driver enforcement as shown below. Click the Start menu and select Settings. Click Update and Security. Click on Recovery. Click Restart now under Advanced Startup. (The computer won't actually restart until after step 8.) Click Troubleshoot. Click Advanced options. Click Startup Settings. Click on Restart. On the Startup Settings screen press 7 or F7 to disable driver signature enforcement. After the computer has finished booting up, run aocl install. Run aocl diagnose to verify that it succeeds Note: If your system has BitLocker enabled, you will need to enter the recovery key between steps 8 and 9 above. You must get the recovery key before starting the above procedure. To get the recovery key, do the following: Run Bitlocker Manager Select “Back up your Recovery Key” Select “Print the recovery key” This problem is scheduled to be fixed in a future version of Quartus.Error: "cannot find board_env.xml in ..."
Description When using Intel® FPGA OpenCL™ SDK 18.1, customer may get error information as "cannot find board_env.xml" during kernel compilation flow when a relative path is used to specify the -board-package parameter. For example: aoc -no-auto-migrate boardtest.cl -o boardtest_a10soc_noautomigrate/boardtest.aocx -board-package=./board/a10soc Resolution To work around this problem use an absolute path for the the board-package. aoc -no-auto-migrate boardtest.cl -o boardtest_a10soc_noautomigrate/boardtest.aocx -board-package=/<quartus installation>/hld/board/a10socWhy does #pragma ivdep not work correctly in aocl version 17.0?
Description In 16.1, this code behaved as expected where the outer loop was serialized due to dependencies and the inner loop dependencies were removed by the #pragma ivdep. // This loop gets serialized due to true dependencies with inner loop for (unsigned char x = 0; x < 4; x ) { // Inner loop does not have inter-iteration dependencies, but depends on outer loop #pragma ivdep for (unsigned char y = 0; y<64; y ) { In 17.0, the #pragma ivdep is now applied to both the inner and outer loop, so the dependencies in the outer loop are not accounted for by the compiler. As a result, similar code may not work correctly in hardware despite working in emulation. Resolution Workaround: 1. Add an extra argument "dummy" to the kernel. On the host side, always pass 1 for this dummy argument. BEFORE __kernel void my_kernel( __global cpx_t* restrict input, __global cpx_t* restrict result) AFTER __kernel void my_kernel( __global cpx_t* restrict input, __global cpx_t* restrict result, int dummy) 2. In the loop nest, wrap the inner loop in "if (dummy)": // This loop gets serialized due to true dependencies for (unsigned char x = 0; x < 4; x ) { if (dummy) { // No dependencies within each set of 64 iterations #pragma ivdep for (unsigned char y = 0; y<64; y ) { This issue is scheduled to be fixed in a future version of the Intel© OpenCL™ for FPGA SDK.Internal Compiler Error: Missing start cycle information for queried node: sync_out
Description You may see this error message when the Intel® FPGA SDK for OpenCL™ compiler executes an autorun kernel. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. Resolution This problem is fixed beginning with the Intel FPGA SDK for OpenCL compiler software version 18.0.Assign LVDS I/O standard-supported pins in right I/O banks of Arria V A1/A3/C3 devices as PLL clock input pins only
Description If you use the Quartus II software version 13.0 DP2 or 13.0 SP1 to create a design that targets an Arria V A1, A3 or C3 device, and you use the LVDS I/O standard-enabled pins in the right I/O bank for purposes other than as phase-locked loop (PLL) clock input pins, the resulting FPGA hardware might not function properly. Resolution You must assign the LVDS I/O standard-enabled pins in the right I/O bank as PLL clock input pins only. The Quartus II software version 13.0 DP2 or 13.0 SP1 does not issue an error message for incorrect assignments to these LVDS I/O standard-enabled pins.
