Why is the waitresponsevalid signal not exported when using the Avalon®-MM Pipeline Bridge FPGA IP when “Use Avalon Transaction Responses” option is enabled?

Description

Due to a problem in the Avalon®-MM Pipeline Bridge FPGA IP, when “Use Avalon Transaction Responses” option enabled, only writeresponse signal is exported, writeresponsevalid is not.

For connections between Avalon-MM masters and Avalon-MM Pipeline Bridge, where write responses are expected by masters, the absence of writeresponsevalid signal will result in potential issues.

Resolution

This problem has been fixed in Intel® Quartus® Prime Pro Edition software version 20.3 and later versions.