Where to get the MAX® 10 FPGA Variable Pitch Ball-Grid Array(VPBGA) 610-pin Package Information?
Description The MAX® 10 VPBGA 610-pin Package Information is not being listed in the FPGA Packaging Device Information. Resolution Download the MAX® 10 VPBGA 610-pin Package Information from the Altera® FPGA 04r-00549-00 Package Mechanical Drawing
Why does the Intel® FPGA Download Cable II driver installation fail on Windows* operating system?
Description Due to the expiration of the digital signature certificate of the Intel® FPGA Download Cable II driver for Windows* operating system, the installation process of the driver may fail. Follow the next steps to verify if the digital signature certificate of your driver has expired: Go to '<Quartus Installation Path>\qprogrammer\quartus\drivers\usb-blaster-ii' folder Right click on 'usbblasterii.cat' and select 'Properties', then select the 'Digital Signatures' tab Select the 'IFDLII Production Key1' signature from the 'Signature List' and click 'Details' Click on 'View Certificate' If the driver has expired, you will see the 'This certificate has expired or is not yet valid' message Resolution To work around this problem, follow the next steps: Download an updated version of the driver from the following link Decompress the downloaded file and substitute 'usb-blaster-ii.inf' and 'usb-blaster-ii.cat' files in '<Quartus Installation Path>\qprogrammer\quartus\drivers\usb-blaster-ii' folder Launch the Windows* 'Device Manager' Locate 'Altera USB-Blaster II (JTAG interface)' node under 'JTAG cables' in the Windows* 'Device Manager', right click and select 'Update Driver' Choose ´'Browse my computer for driver software' then click on 'Search for drivers in this location' and point to the new 'usb-blaster-ii.inf' file This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1.Internal Error: Sub-system: PVAFAM_VISITOR, File: /quartus/power/pvafam/pvafam_arm_cycloneii_visitor_common.cpp, Line: 1491
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 18.1 and earlier, you may see this internal error when you generate an Early Power Estimator (EPE) file or run Power Analyzer. Resolution To work around this problem, disable vectorless toggle rate analysis in the Power Analyzer Settings and recompile the project.Is the Intel® Quartus® Prime Programmer option "Unprotect EPCS/EPCQ devices selected for the erase/program operation" valid for third party flash devices?
Description The Intel® Quartus® Prime Programmer option "Unprotect EPCS/EPCQ devices selected for the erase/program operation" is valid for Micron MT25Q and Macronix MX25 and MX66U series flash devices. For Cypress S25FL flash devices, the Intel Quartus Prime programmer will always remove the block protection bits. For other third party flash devices, refer to the Generic Flash Programmer to customize the programming flow to remove the block protection bits. Genetic Flash Programmer User Guide: Intel Quartus Prime Standard Edition Genetic Flash Programmer User Guide: Intel Quartus Prime Pro EditionCan the MMR interface be used in conjunction with the Efficiency Monitor in the External Memory Interface Intel® FPGA IP?
Description Due to a restriction in the Intel® Quartus® Prime Edition Software, it is not possible to enable the Memory Mapped Configuration and Status Register (MMR) interface in conjunction with the Efficiency Monitor when implementing DDR3 or DDR4 interfaces using the External Memory Interface Intel FPGA IP for Intel® Arria® 10, Intel® Cyclone® 10 GX or Intel® Stratix® 10 devices. Enabling both options will result in an error like that shown below : Error: Interface must have an associated clock Resolution There is no planned fix for this restriction.Why does Questa* license fail to install in the Quartus® Prime Lite Edition Software version 24.1?
Description This problem is due to user setup changed to new NIC ID. The license does not match the current NIC ID. Resolution To workaround this problem, you need to regenerate the license using new NIC ID then update the environment variable method and restart the computer to get the license to operate properly.How can I program the UFM with a hex/mif in Intel® MAX® 10 devices without impacting the CFM?
Description To program the User Flash Memory (UFM) with hex/mif in Intel® MAX® 10 devices without impacting the Configuration Flash Memory (CFM), do the following. Resolution Open the Convert Programming Files utility in Intel Quartus® Prime software Choose internal configuration in mode category. Go to Options/Boot info and select UFM source as load memory file. Choose a File path for your .hex or .mif file. After this process, add the SOF file to the main conversion window and generate *.pof file. Open Intel Quartus Prime Programmer. After proper recognition of the Intel MAX® 10 device, add the previously generated *.pof file and set Program / Configuration to UFM (only).Why I fail to generate a .jbc file with REAL_TIME_ISP enable using quartus_cpf command in Intel® Quartus® Prime Software version 22.3?
Description You will not able to generate a .jbc file with ISP_REAL_TIME feature if using quartus_cpf command in Intel® Quartus® Prime Software version 22.3 and below. This is because there is problem with quartus_cpf internal script which unable to include the ISP_REAL_TIME feature into the generated .jbc file. Resolution This problem is fixed starting from Intel® Quartus® Prime Software version 22.4.Error: No spd files are included in quartus project
Description In the Intel® Quartus® Prime Standard Edition Software version 17.1, the error message above may be seen while executing the ip-setup-simulation script on a project targeting a device that doesn't belong to the Intel® Arria® 10, Intel® Stratix® 10, or Intel® Cyclone® 10 families. The ip-setup-simulation script requires an Intel® Arria® 10, Intel® Stratix® 10, or Intel® Cyclone® 10 Platform Designer folder structure to work properly. Resolution To work around this problem, switch from using the ip-setup-simulation script to the ip-make-simscript script. For more information on the ip-make-simscript script usage, please consult the Intel® Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis, page 255.Why EMAC0 of Cyclone® V SOC HPS is not counting packets like EMAC1?
Description Due to a problem in the Cyclone® V SoC HPS, EMAC0 is not constantly counting the incoming packets as EMAC1 does. Some packets might be lost in counting. However, they have been received by the system. Resolution To work around this problem in the Cyclone® V SoC HPS EMAC0, you need to follow the steps below: 1- Operate the RxFIFO in the store-and-forward mode. 2- Operation_Mode Register: located at the address: 0xFF701018 (for EMAC0) 0xFF703018 (for EMAC1) Set bit 25 (“rsf” bit) to 0x1
