Knowledge Base Article
Why is the LPM_PIPELINE parameter in the LPM_CLSHIFT FPGA IP recognized in simulation but ignored in synthesis from Quartus® Prime Pro Edition Software 23.3 onwards?
Description
Due to architectural revisions to the LPM_CLSHIFT FPGA IP starting with Quartus® Prime Pro Edition Software version 23.3, as a result of these changes, the LPM_PIPELINE parameter has been deprecated. Although these parameters remain configurable through the IP Parameter Editor, they will no longer be recognized or utilized by the software and are effectively ignored. This change has led to discrepancies between the simulation models, which continue to acknowledge the Pipeline parameters, and the implemented design, where they are ignored.
Resolution
As a temporary solution, it is necessary to manually instantiate the pipeline registers within your design to preserve the intended functionality for implementation while ensuring they are disabled during simulation. Below, you will find pipeline registers and instantiation templates for both Verilog and VHDL. These are conditioned by a SIMULATION user-defined parameter, providing flexibility to enable or disable the modules as required. Feel free to use these templates as a starting point for your manual implementation.
Verilog Register Pipeline Template:
module pipeline_registers #(
parameter DATA_WIDTH = 8 // Set the default data width
)(
input wire clk, // Clock input
input wire [DATA_WIDTH-1:0] data_in, // Data input
output wire [DATA_WIDTH-1:0] data_out // Data output
);
// Intermediate pipeline stage (registers)
reg [DATA_WIDTH-1:0] pipeline_stage;
always @(posedge clk) begin
// Shift data through the pipeline
pipeline_stage <= data_in;
end
assign data_out = pipeline_stage;
endmodule
Verilog Instantiation Template:
// Instantiate the pipeline_registers module
generate
if (SIMULATION == 1'b1) begin : simulation_only
// bypass the pipeline module
assign data_out_signal = data_in_signal;
end
endgenerate
generate
if (SIMULATION == 1'b0) begin : synthesis_only
// instantiation template for the pipeline module
pipeline_registers #(
.DATA_WIDTH(16) // Specify the data width for this instance
) pipeline_registers_inst (
.clk(clk), // Connect to system clock
.data_in(data_in_signal), // Connect to input data signal
.data_out(data_out_signal) // Connect to output data signal
);
end
endgenerate
VHDL Register Pipeline Template:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; -- For using unsigned types
entity pipeline_registers is
generic (
DATA_WIDTH : integer := 8 -- Set the default data width
);
port (
clk : in STD_LOGIC; -- Clock input
data_in : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); -- Data input
data_out : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0) -- Data output
);
end entity pipeline_registers;
architecture Behavioral of pipeline_registers is
-- Intermediate pipeline stages (registers)
signal pipeline_stage : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
-- Shift data through the pipeline
pipeline_stage <= data_in;
end if;
end process;
data_out <= pipeline_stage;
end architecture Behavioral;
VHDL Instantiation Template:
-- Instantiate the pipeline_registers entity
Simulation_only : if SIMULATION generate
-- bypass the pipeline module
data_out_signal <= data_in_signal; -- Connect to input and output data signals
end generate;
synthesis_only : if not SIMULATION generate
-- instantiation template for the pipeline module
pipeline_registers_inst : entity work.pipeline_registers
generic map (
DATA_WIDTH => 16 -- Specify the data width for this instance
)
port map (
clk => clk, -- Connect to system clock
data_in => data_in_signal, -- Connect to input data signal
data_out => data_out_signal -- Connect to output data signal
);
end generate;
Please ensure these templates' signal names and widths match your design specifications. Adjust the DATA_WIDTH parameter or generic as needed to fit the width of the data you are working on in your design.