Why is the IRQ_HPD of the DisplayPort Intel® FPGA IP asserted before link training?

Description

The DisplayPort Intel® FPGA IP Sink may assert CR_Lock before link training, and the pseudo-CR_Lock generates pseudo IRQ_HPD before link training. Because CR_Lock and IRQ_HPD are supposed to be valid only during and after link training, the DisplayPort Intel® FPGA IP Source should ignore the pseudo-IRQ_HPD.

Resolution

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 17.1.