Why is the delay inconsistent for the pX_reset_status_n_o signal de-assertion following a pin_perst_n event?

Description

The pX_reset_status_n_o signal from the P-Tile Avalon® Streaming IP for PCI* Express includes an accumulative characteristic related to the number of back to back pin_perst_n assertions.

Each back-to-back pin_perst_n event will be queued, and executed one after the other, affecting the total time it takes for the P-Tile Avalon® Streaming IP for PCI* Express to come out of reset and de-assert the pX_reset_status_n_o signal.

Figure 1. shows the P-Tile Avalon® Streaming IP for PCI Express behavior when a single pin_perst_n assertion is issued from the host. Figure 2. shows the accumulative characteristic when multiple pin_perst_n assertions are issued.

Resolution

The P-Tile Avalon® Streaming IP for PCI* Express User Guide will not be updated to include this information.