Why does the Quartus® Prime Pro Edition Software report a pin placement error when Customize Pin Selections is disabled in the LVDS SERDES IP?

Description

When using the LVDS SERDES IP with Agilex® 5 FPGAs or Agilex® FPGA 7 M-Series FPGAs, the physical byte and pin assignment must match the pin index specified under the Pin Settings tab in the IP Catalog GUI. If a physical byte or pin is selected without matching the corresponding pin index, the Quartus® Prime Pro Edition Software may report a pin-placement or compilation error.

Even when Customize Pin Selections is not selected, each pin must be assigned according to the default byte and pin values specified for its corresponding pin index in the Pin Settings tab. Not selecting this option does not allow arbitrary byte or pin assignments.

To use a different byte and pin assignment, select Customize Pin Selections and manually assign the byte and pin locations according to the design requirements and the supported device pin mapping.

Resolution

To avoid this problem, assign the LVDS SERDES IP pins according to the specified pin index in the Pin Settings tab; to use a different byte and pin assignment, select Customize Pin Selections and manually assign the byte and pin locations according to the design requirements.