Why does the GTS JESD204B/C FPGA IP and Design Example generation fail on Agilex™ 3 FPGA and Agilex™ 5 FPGA devices when selecting System or HVIO PLL clocking mode?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter an error message like the following when generating the GTS JESD204B/C FPGA IP Design Example.  

"Error: phy_inst.inst_directphy: System/HVIO PLL frequency "307.2" cannot be smaller than transceiver's parallel clock frequency "858.0"   

The following IP configuration steps may lead to the above error:   

1. Set the Data rate to a specific value
2. Set the Datapath clocking mode System PLL
3. Enable the example design generation
4. Enable Simulation and/or Synthesis in the Example Design Files section
5. Increase the data rate to a value higher than the data rate set in step 1
6. Generate the IP or Example Design

*Note that this problem will not occur when you use a data rate set in Step 5 lower than the data rate set in Step 1. 

Resolution

 When you encounter this error, use the following workaround:

1.  Disable example design generation
2. Update the System PLL frequency for the latest data rate
3. Enable example design generation
4. Generate the IP or Example Design

This problem will be fixed in a future release of the Quartus Prime Pro Edition Software.