Why does the External Memory Interfaces Intel® FPGA IP encounter a fitter compilation error when an I/O lane does not have all 12 pins bonded out?

Description

You may encounter a fitter compilation error in the Intel® Quartus® Prime software if the External Memory Interfaces Intel Arria® 10 FPGA IP or External Memory Interfaces Intel Cyclone® 10 GX FPGA IP has a DQ group placed in an I/O lane that contains unbonded FPGA I/O pins.  

Resolution

To work around this problem, you need to ensure the External Memory Interfaces Intel®Arria® 10 FPGA IP or External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP DQ group is placed in an I/O lane where all 12 pins are bonded out.