Why does the Agilex™3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, fail during simulation using Xcelium* and Riviera*-PRO simulators in Quartus® Prime Pro Edition Software version 25.1.1?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1, the Agilex™ 3 FPGA and Agilex™ 5 FPGA Triple-Speed Ethernet IP Design Example, when configured with IEEE 1588v2, may fail during simulation of the design example testbench.
The following behaviors may be observed:

• Riviera*-PRO: Simulation may hang or display "Error: Accuracy criteria not met".
• Xcelium*: Simulation may pass, but accuracy criteria will not be met, leading to incorrect results.

Resolution

There is no workaround to this problem in the Quartus® Prime Pro Edition Software Version 25.1.1.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.