Why does the 25G Ethernet Intel® FPGA IP core Design Example with IEEE 1588v2 feature enabled halt in Xcelium* and NCSim* Simulators?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2, you may see the 25G Ethernet Intel® FPGA IP core design example with IEEE 1588v2 feature enabled halt in Xcelium* and NCSim* Simulators.

Resolution

 To work around this problem when using Intel® Quartus® Prime Pro Edition v19.2 software, use other simulators available in the example design, such as Mentor* ModelSIM* or Synopsys* VCS* simulators. 

This problem is fixed starting from Intel® Quartus® Prime Pro Edition v20.3 software onwards.