Why does Nios® V Processor FPGA IP encounter Error(20327) when performing an IP upgrade?

Description

This issue may be seen in the Quartus® Prime Pro Edition Software starting from software version 22.1 when running Nios® V Processor Intel® FPGA IP upgrade from designs created in earlier versions of Quartus® Prime Pro Edition Software.

This is due to a problem in Platform Designer, which does not automatically update the Nios® V Processor FPGA IP during FPGA IP Upgrade.

Error(20327) from processor update in software version 22.1:
Error(20327): Error: cpu.cpu: "Reset Agent" (resetSlave) "ram.s1" is out of range: "Absolute"
Error(20327): Error: cpu.cpu: "Exception Agent" (exceptionSlave) "ram.s1" is out of range: "Absolute"
Error(20327):  Error: sys: File cpu.ip declares port dbg_reset_reset which is missing in entity cpu

Error(20327) from processor update in software version 23.3:
Error(20327): Error: cpu declares port data_manager_awsize which is missing in file cpu.ip 
Error(20327): Error: cpu declares port instruction_manager_arsize which is missing in file cpu.ip 
Error(20327): Error: cpu declares port instruction_manager_awsize which is missing in file cpu.ip 
Error(20327): Error: cpu declares port data_manager_arsize which is missing in file cpu.ip 
Error(20327): Error: cpu declares port instruction_manager_wlast which is missing in file cpu.ip 
Error(20327): Error: cpu declares port data_manager_wlast which is missing in file cpu.ip 

 

Resolution

To workaround this problem, follow the steps below:
1.    Open the affected Platform Designer system and click Sync System Infos to upgrade the design to the latest IP version.
2.    Right-click the Nios® V Processor and click the Replace option.
3.    Replace the outdated processor core with the latest processor core.
4.    Configure the same processor settings and interface connections.
5.    Resolve any design errors after synchronizing the system component information.
6.    Generate design HDL and exit the Platform Designer.
7.    Proceed to relaunch the IP Upgrade Tool.
8.    Remove the outdated IP file from the Project Navigation.
9.    Compile the design.

Note: In the Quartus® Prime Standard Edition Software, the processor core needs to be removed and re-instantiated manually.
For more information, refer to the Nios® V Processor FPGA IP Release Notes and the Quartus® Prime Pro Edition Software Platform Designer User Guide.