Why does internal serial loopback test results fail when running the GTS JESD204B FPGA IP Design Example on Agilex™ 3 FPGA or Agilex™ 5 FPGA hardware?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may encounter a failed test result when running the internal serial loopback test with the GTS JESD204B FPGA IP Design Example. 

Resolution

To work around this problem in the Quartus® Prime Pro Edition Software versions 25.3, download and install patch below.

After installing the patch, do the following: 

1. In the GTS JESD204B IP GUI editor, IP > Main tab, enabled the following checkboxes:  
   1. Enable PMA Avalon memory-mapped interface  
   2. Enable control and status registers  
2.  Depending on the data rate, configure the IP ➤ Analog Parameters ➤ Analog Rx ➤RX Adaptation mode:  
   1. Manual: if data rate <= 7Gbps 
   2. Auto: if data rate > 7Gbps 
3. Regenerate the design example. 

This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.