Why are ECC error flags observed when testing the Interlaken (2nd Generation) Intel® FPGA IP core on hardware?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier, the Interlaken (2nd Generation) Intel® FPGA IP core fails to gate the error correction code (ECC) error with the data valid signal, hence ECC errors may be incorrectly reported.

Resolution

No workaround to this problem exists when using the Intel® Quartus® Prime Pro Edition Software version 21.4 and earlier.
This problem has been fixed starting in version 22.1 of the Intel® Quartus® Prime Pro Edition Software.